HYB18L256160B QIMONDA [Qimonda AG], HYB18L256160B Datasheet - Page 29
HYB18L256160B
Manufacturer Part Number
HYB18L256160B
Description
DRAMs for Mobile Applications 256-Mbit Mobile-RAM
Manufacturer
QIMONDA [Qimonda AG]
Datasheet
1.HYB18L256160B.pdf
(58 pages)
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1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
Rev. 1.73, 2006-09
01302004-CZ2R-J9SE
Parameter
DQ and DQM input setup time
DQ input hold time
DQM input hold time
DQM write mask latency
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE to PRECHARGE command period
WRITE recovery time
PRECHARGE command period
no. of clock cycles = specified delay / clock period; round up to next integer.
t
t
t
t
t
t
t
t
IS
IH
DQW
RC
RCD
RAS
WR
RP
Symbol
29
1.5
0.8
0.5
0
67
19
45
14
19
min.
- 7.5
—
—
—
—
—
—
100k
—
—
WRITE Burst (CAS Latency = 2)
Timing Parameters for WRITE
max.
HY[B/E]18L256160B[C/F]L-7.5
256-Mbit Mobile-RAM
ns
ns
ns
t
ns
ns
ns
ns
ns
CK
Units
FIGURE 25
TABLE 13
Data Sheet
—
—
—
—
1)
1)
1)
1)
1)
Note