HYB18M256160CF-6/7.5 QIMONDA [Qimonda AG], HYB18M256160CF-6/7.5 Datasheet
HYB18M256160CF-6/7.5
Related parts for HYB18M256160CF-6/7.5
HYB18M256160CF-6/7.5 Summary of contents
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... HYB18M256320CF–6/7.5, HYE18M256320CF–6/7.5, HYB18M256160CF–6/7.5 , HYE18M256160CF–6/7.5 Revision History: Rev.1.44, 2007-07 Page Subjects (major changes since last revision) All Adapted Internet Edition 55, 56 Editorial changes Previous Revision:Rev.1.43, 2007-04 24 Updated Figure 44 for 60-ball PG-VFBGA-60-4 (x16) 25 Updated Figure 45 for 90-ball PG-VFBGA-90-3 (x32) Previous Revision:Rev ...
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Overview 1.1 Features • Organization: – 4 banks × 4 Mbit × 16 page size – 4 banks × 2 Mbit × 32 page size • Double-data-rate architecture: two data transfers per clock cycle • ...
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... Rows Columns 1) Type Package Standard Temperature Range HYB18M256320CF–6/7.5 90–ball PG-VFBGA-60-3 HYB18M256160CF–6/7.5 60–ball PG-VFBGA-60-4 Extended Temperature Range HYE18M256320CF–6/7.5 90–ball PG-VFBGA-60-3 HYE18M256160CF–6/7.5 60–ball PG-VFBGA-60-4 1) HY[B/E]: Designator for memory products (HYB: Standard temp. range, HYE: Extended temp. range) 18M: 1.8V DDR Mobile-RAM ...
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Pin Configuration Rev.1.44, 2007-07 06262007-JK8G-48BV Standard Ballout 256-MBit x16 DDR Mobile-RAM (Top View 60-ball) Standard Ballout 256-MBit x32 DDR Mobile-RAM (Top View 90-ball) 5 Internet Data Sheet HY[B/E]18M256[16/32]0CF 256-Mbit DDR Mobile-RAM FIGURE 1 FIGURE 2 ...
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... Description The HY[B/E]18M256[16/32]0CF is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits internally configured as a quad-bank DRAM. The HY[B/E]18M256[16/32]0CF uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate architecture is essentially a 2n pre fetch architecture, with an interface designed to transfer two or four data words per clock cycle at the I/O pins ...
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... Address Inputs: Provide the row address for ACTIVE commands and the column address and Auto A0 - A11 (x32) Precharge bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 (=AP) is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A10=LOW) or all banks (A10=HIGH) ...
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... Functional Description The DDR Mobile-RAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits internally configured as a quad-bank DRAM. READ and WRITE accesses to the DDR Mobile-RAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, followed by a READ or WRITE command ...
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Register Definition 2.1.1 Mode Register The Mode Register is used to define the specific mode of operation of the DDR Mobile-RAM. This definition includes the selection of a burst length (bits A0-A2), a burst type (bit A3) and a ...
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Extended Mode Register The Extended Mode Register controls additional low power features of the device. These include the Partial Array Self Refresh (PASR), the Temperature Compensated Self Refresh (TCSR) and the drive strength selection for the DQs. The Extended ...
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Function Truth Tables CKEn-1 CKEn Current State L L Power-Down Self Refresh Deep Power-Down L H Power-Down Self Refresh Deep Power-Down H L All Banks Idle Bank(s) Active All Banks Idle All Banks Idle H H See Table 6 ...
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Current State CS RAS CAS WE Write (Auto Precharge Disabled This table applies when CKEn-1 was HIGH and CKEn is HIGH (see POWER-DOWN or SELF REFRESH). 2) This table is ...
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Current State CS RAS CAS WE Any Idle Row Activating Active Precharging Read (Auto Precharge ...
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Electrical Characteristics 3.1 Operating Conditions Parameter Power Supply Voltage Power Supply Voltage for Output Buffer Input Voltage Output Voltage Operation Case Temperature Storage Temperature Power Dissipation Short Circuit Output Current Attention: Stresses above those listed here may cause permanent ...
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Parameter Power Supply Voltage Power Supply Voltage for DQ Output Buffer Input leakage current Output leakage current Address and Command Inputs (BA, BA1, CKE, CS, RAS, CAS, WE) Input high voltage Input low voltage Clock Inputs (CK, CK) DC input ...
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AC Characteristics Parameter DQ output access time from CK/CK DQS output access time from CK/CK Clock high-level width Clock low-level width Clock half period Clock cycle time and DM input fast slew ...
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Parameter Read preamble Read postamble ACTIVE to PRECHARGE command period ACTIVE to ACTIVE command period AUTO REFRESH to ACTIVE/AUTO REFRESH command period ACTIVE to READ or WRITE delay Col address to col address delay ...
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DQSQ 18) The specific requirement is that DQS be valid (HIGH, LOW, or some point on ...
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Operating Currents Parameter & Test Conditions Operating one bank active-precharge current CKE is HIGH HIGH between valid RC RCmin CK CKmin commands; address inputs are SWITCHING; data bus inputs ...
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Parameter & Test Conditions Self refresh current: CKE is LOW LOW HIGH; address and control inputs are STABLE; data bus inputs are STABLE Deep Power Down current 1) 0 °C ≤ T ≤ 70 °C (comm.); ...
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Package Outlines Notes 1. Solder ball attach fiducial (SBA) 2. Middle of package edges 3. Package orientation mark A1 4. Bad unit marking (BUM) 5. Tolerances regarding ISO 2768-mK 6. Dimensions in mm Rev.1.44, 2007-07 06262007-JK8G-48BV HY[B/E]18M256[16/32]0CF 256-Mbit DDR ...
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Notes 1. Solder ball attach fiducial (SBA) 2. Middle of package edges 3. Package orientation mark A1 4. Bad unit marking (BUM) 5. Tolerances regarding ISO 2768-mK 6. Dimensions in mm Rev.1.44, 2007-07 06262007-JK8G-48BV HY[B/E]18M256[16/32]0CF 256-Mbit DDR Mobile-RAM 90–ball PG-VFBGA-60-3 ...
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List of Figures Figure 1 Standard Ballout 256-MBit x16 DDR Mobile-RAM (Top View 60-ball ...
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... List of Tables Table 1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 2 Memory Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 4 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5 Truth Table - CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 6 Current State Bank n - Command to Bank Table 7 Current State Bank n - Command to Bank m (different bank Table 8 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 9 Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 10 Electrical Characteristics ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Edition 2007-07 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 München, Germany © Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or ...