HYB25D512160BC-6 QIMONDA [Qimonda AG], HYB25D512160BC-6 Datasheet
HYB25D512160BC-6
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HYB25D512160BC-6 Summary of contents
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HYB25D512[40/80/16]0B[C/T](L), HYB25D512[40/80/16]0B[E/F](L) Revision History: 2006-09, Rev. 1.63 Page Subjects (major changes since last revision) All Qimonda update All Adapted internet edition Previous Revision: 2005-10, Rev. 1.62 We Listen to Your Comments Any information within this document that you feel is ...
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Overview This chapter gives an overview of the 512-Mbit Double-Data-Rate SDRAM product family and describes its main characteristics 1.1 Features • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and ...
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... DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is edge-aligned with data for Reads and center-aligned with data for Writes. The 512-Mbit Double-Data-Rate SDRAM operates from a differential clock (CK and CK ...
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... HYB25D512800BC–5 ×16 HYB25D512160BC–5 ×4 HYB25D512400BC–6 2.5-3-3 ×8 HYB25D512800BC–6 ×16 HYB25D512160BC–6 1) HYB: designator for memory components V 25D: DDR SDRAMs at = 2.5 V DDQ 512: 512-Mbit density 400/800/160: Product variations x4, ×8 and ×16 B: Die revision B C/F/E/T: Package type FBGA and TSOP L: Low power (on request) Rev ...
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Part Number Org. CAS-RCD-RP Latencies ×4 HYB25D512400BF–5 3.0-3-3 ×8 HYB25D512800BF–5 ×16 HYB25D512160BF–5 ×4 HYB25D512400BF–6 2.5-3-3 ×8 HYB25D512800BF–6 ×16 HYB25D512160BF–6 ×4 HYB25D512400BE–5 3.0-3-3 ×8 HYB25D512800BE–5 ×16 HYB25D512160BE–5 ×4 HYB25D512400BE–6 2.5-3-3 ×8 HYB25D512800BE–6 ×8 HYB25D512800BEL–6 ×16 HYB25D512160BE–6 ×16 HYB25D512160BEL–6 ×4 HYB25D512400BE–7 Rev. ...
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Pin Configuration The pin configuration of a DDR SDRAM is listed by function in column are explained in Table 5 and Table 6 TSOP package in Figure 2 Ball#/Pin# Name Pin Type Clock Signals G2 G3, ...
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Ball#/Pin# Name Pin Type Data Signals ×4 organization B7, 5 DQ0 I/O D7, 11 DQ1 I/O D3, 56 DQ2 I/O B3, 62 DQ3 I/O Data Strobe ×4 organisation E3, 51 DQS I/O Data Mask ×4 organization F3 ...
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Ball#/Pin# Name Pin Type Data Strobe ×16 organization E3, 51 UDQS I/O E7, 16 LDQS I/O Data Mask ×16 organization F3, 47 UDM I F7, 20 LDM I Power Supplies V F1 REF V A9, B2, C8, D2, ...
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Ball#/Pin# Name Pin Type F9, 14, 17, 19 25,43, 50, 53 Abbreviation Description I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I/O is ...
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Pin Configuration P-TFBGA-60 Top View, see the balls throught the package Rev. 1.63, 2006-09 03062006-PFFJ-YJY2 ...
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Rev. 1.63, 2006-09 03062006-PFFJ-YJY2 HYB25D512[40/16/80]0B[E/F/C/T](L) Double-Data-Rate SDRAM Pin Configuration P-TSOPII-66 ...
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... I/O pins. Rev. 1.63, 2006-09 03062006-PFFJ-YJY2 Read and write accesses to the DDR SDRAM are burst memory containing oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command ...
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Field Bits Type Description BL [2:0] w Burst Length Number of sequential bits per DQ related to one read/write command. Note: All other bit combinations are RESERVED. 001 2 B 010 4 B 011 Burst ...
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Burst Length Starting Column Address ...
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Field Bits Type Description DLL 0 w DLL Status Drive Strength MODE [12:2] w Operating Mode Note: All other bit combinations are RESERVED Rev. 1.63, 2006-09 03062006-PFFJ-YJY2 ...
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Name (Function) Deselect (NOP) No Operation (NOP) Active (Select Bank And Activate Row) Read (Select Bank And Column, And Start Read Burst) Write (Select Bank And Column, And Start Write Burst) Burst Terminate Precharge (Deactivate Row In Bank Or Banks) ...
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Current State CKE n-1 CKEn Previous Current Cycle Cycle Self Refresh L L Self Refresh L H Power Down L L Power Down L H All Banks Idle H L All Banks Idle H L Bank(s) Active ...
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Current State CS RAS CAS WE Any Idle Row Active ...
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Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank. 11) Requires appropriate DM masking. Rev. 1.63, 2006-09 03062006-PFFJ-YJY2 HYB25D512[40/16/80]0B[E/F/C/T](L) Double-Data-Rate SDRAM 20 Internet Data Sheet ...
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Truth Table 4: Current State Bank n - Command to Bank m (different bank) Current State CS RAS CAS WE Any Idle Row Activating Active, or Pre L ...
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Concurrent Auto Precharge: This device supports “Concurrent Auto Precharge”. When a read with auto precharge or a write with auto precharge is enabled any command may follow to the other banks as long as that command does not interrupt ...
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Electrical Characteristics 4.1 Operating Conditions Parameter V Voltage on I/O pins relative Voltage on inputs relative Voltage on supply relative Voltage on supply relative to DDQ SS ...
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Parameter Input Capacitance: CK, CK Delta Input Capacitance Input Capacitance: All other input-only pins Delta Input Capacitance: All other input-only pins Input/Output Capacitance: DQ, DQS, DM Delta Input/Output Capacitance: DQ, DQS These values are guaranteed by design and ...
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Parameter Symbol V Device Supply Voltage DD V Device Supply Voltage DD V Output Supply Voltage DDQ V Output Supply Voltage DDQ V EEPROM supply voltage DDSPD V Supply Voltage, I/O Supply , SS V Voltage SSQ V Input Reference ...
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AC Characteristics (Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, Specifications and Conditions, and Electrical Characteristics and AC Timing.)Note Note V 1. All voltages referenced Tests for ...
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Parameter Symbol t DQ output access time from AC CK/ high-level width CH t Clock cycle time low-level width CL t Auto precharge write recovery + DAL precharge time t DQ and DM input hold ...
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Parameter Symbol t Address and control input setup IS time t Data-out low-impedance time LZ from CK/CK t Mode register set command cycle MRD time t DQ/DQS output hold time QH t Data hold skew factor QHS t Active to ...
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These parameters are not referred to a specific HZ LZ voltage level, but specify when the device is no longer driving (HZ), or begins ...
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Parameter Mode register set command cycle time DQ/DQS output hold time Data hold skew factor Active to Read w/AP delay Active to Precharge command Active to Active/Auto-refresh command period Active to Read or Write delay Average Periodic Refresh Interval Auto-refresh ...
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Parameter Operating Current: one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating Current: one bank; active/read/precharge; Burst = 4; Refer to the following page ...
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DDR266A DDR333 Symbol Typ. Max. Typ DD0 DD1 90 110 105 I 1.5 4 1.6 DD2P DD2F DD2Q I ...
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Package Outlines There are two package types used for this product family each in lead-free and lead-containing assembly: • P-TFBGA: Plastic Thin Fine-Pitch Ball Grid Array Package Description Ball Size Recommended Landing Pad Recommended Solder Mask • P-TSOPII: Plastic ...
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Basic +0.1 0.35 -0.05 22.22 Lead 1 Rev. 1.63, 2006-09 03062006-PFFJ-YJY2 Package Outline of P-TSOPII-66-1 (Lead-Free/Lead-Containing) Gage Plane 0.805 REF 0.1 Seating Plane ±0.13 34 Internet Data Sheet HYB25D512[40/16/80]0B[E/F/C/T](L) Double-Data-Rate SDRAM FIGURE 5 10.16 ±0.13 0.5 ±0.1 11.76 ±0.2 ...
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List of Figures Figure 1 Pin Configuration P-TFBGA-60 Top View, see the balls throught the package . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Edition 2006-09 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 München, Germany © Qimonda AG 2006. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or ...