HYB25DC128160C QIMONDA [Qimonda AG], HYB25DC128160C Datasheet
HYB25DC128160C
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HYB25DC128160C Summary of contents
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... HYB25DC128800C[E/F], HYB25DC128160C[E/F] Revision History: 2007-01, Rev. 1.1 Page Subjects (major changes since last revision) All Qimonda update All Adapted internet edition Previous Revision: 2005-07, Rev. 1.0 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. ...
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... The 128-Mbit Double-Data-Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits internally configured as a quad-bank DRAM. The 128-Mbit Double-Data-Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins ...
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... HYB25DC128160CF-5 ×8 HYB25DC128800CE–6 2.5-3-3 ×16 HYB25DC128160CE–6 ×8 HYB25DC128800CF–6 ×16 HYB25DC128160CF–6 1) HYB: designator for memory components V 25DC 2.5 V DDQ 128: 128-Mbit density 800/160: Product variations ×8 and ×16 C: Die revision C F/E: Package type TSOP and FBGA L: Low power version (available on request) - these components are specifically selected for low ...
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Pin Configuration The pin configuration of a DDR SDRAM is listed by function in column are explained in Table 4 and Table 5 TSOP package in Figure 2. Ball#/Pin# Name Pin Type Clock Signals G2 G3, ...
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Ball#/Pin# Name Pin Type Data Signals ×4 Organization B7, 5 DQ0 I/O D7, 11 DQ1 I/O D3, 56 DQ2 I/O B3, 62 DQ3 I/O Data Strobe ×4 Organisation E3, 51 DQS I/O Data Mask ×4 Organization F3 ...
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Ball#/Pin# Name Pin Type Data Strobe ×16 organization E3, 51 UDQS I/O E7, 16 LDQS I/O Data Mask ×16 organization F3, 47 UDM I F7, 20 LDM I Power Supplies V F1 REF V A9, B2, C8, D2, ...
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Ball#/Pin# Name Pin Type F9, 14, 17, 19 25,43, 50, 53 Abbreviation Description I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I/O is ...
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Pin Configuration PG-TFBGA-60 Top View, see the balls through the package Rev. 1.1, 2007-01 03062006-JXUK-E7R1 ...
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Rev. 1.1, 2007-01 03062006-JXUK-E7R1 HYB25DC128[800/160]C[E/F] 128-Mbit Double-Data-Rate SDRAM Pin Configuration PG-TSOPII-66 10 Internet Data Sheet FIGURE 2 ...
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Functional Description 1) Field Bits Type Description BL [2:0] W Burst Length Number of sequential bits per DQ related to one read/write command. Note: All other bit combinations are RESERVED. 001 2 B 010 4 B 011 8 B ...
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Burst Length Starting Column Address ...
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Field Bits Type Description DLL 0 w DLL Status Drive Strength MODE [11:2] Operating Mode 0000000000 Notes 1. A2 must provide compatibility with early DDR devices ...
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Name (Function) Deselect (NOP) No Operation (NOP) Active (Select Bank And Activate Row) Read (Select Bank And Column, And Start Read Burst) Write (Select Bank And Column, And Start Write Burst) Burst Terminate Precharge (Deactivate Row In Bank Or Banks) ...
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Current State CKE n-1 CKEn Previous Cycle Current Cycle Self Refresh L L Self Refresh L H Power Down L L Power Down L H All Banks Idle H L All Banks Idle H L Bank(s) Active ...
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This table applies when CKE n-1 was HIGH and CKE n is HIGH (see was self refresh). 2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are ...
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Current State CS RAS CAS WE Read (With Auto Precharge Write (With Auto Precharge This ...
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Electrical Characteristics 4.1 Operating Conditions Parameter V Voltage on I/O pins relative Voltage on inputs relative Voltage on supply relative Voltage on supply relative to DDQ SS ...
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Parameter Symbol V Device Supply Voltage DD V Device Supply Voltage DD V Output Supply Voltage DDQ V Output Supply Voltage DDQ V V Supply Voltage, I/O Supply , SS SSQ Voltage V Input Reference Voltage REF V I/O Termination ...
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AC Characteristics (Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, Specifications and Conditions, and Electrical Characteristics and AC Timing.) Notes V 1. All voltages referenced Tests ...
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Parameter Input High (Logic 1) Voltage, DQ, DQS and DM Signals Input Low (Logic 0) Voltage, DQ, DQS and DM Signals Input Differential Voltage, CK and CK Inputs Input Closing Point Voltage, CK and CK Inputs V = 2.5 V ...
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Parameter Symbol t DQ and DM input setup time DS t DQS falling edge hold time from DSH CK (write cycle) t DQS falling edge to CK setup DSS time (write cycle) t Clock Half Period HP t Data-out high-impedance ...
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Parameter Symbol t Write postamble WPST t Write recovery time WR t Internal write to read command WTR delay t Exit self-refresh to non-read XSNR command t Exit self-refresh to read command XSRD 1) 0 °C ≤ ≤ 70 °C; ...
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Parameter Operating Current: one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating Current: one bank; active/read/precharge; Burst = 4; Refer to the following page ...
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Symbol –5 DDR400B I 90 DD0 90 I 100 DD1 110 I 5 DD2P I 36 DD2F I 28 DD2Q I 18 DD3P I 45 DD3N 54 I 100 DD4R 120 I 105 DD4W 130 I 190 DD5 I 3.0 ...
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I 4.3 Current Measurement Conditions DD Legend Activate Read Read with Autoprecharge Precharge NOP or DESELECT I : Operating Current: One Bank Operation DD1 1. General test condition t a) ...
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Package Outlines There are two package types used for this product family in lead-free assembly: • PG-TSOPII: Plastic Thin Small Outline Package Type II • PG-TFBGA: Plastic Thin Fine-Pitch Ball Grid Array Package Description Ball Size Recommended Landing Pad ...
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Rev. 1.1, 2007-01 03062006-JXUK-E7R1 HYB25DC128[800/160]C[E/F] 128-Mbit Double-Data-Rate SDRAM Package Outline of PG-TFBGA-60 28 Internet Data Sheet FIGURE 5 ...
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List of Figures Figure 1 Pin Configuration PG-TFBGA-60 Top View, see the balls through the package . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Edition 2007-01 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 München, Germany © Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or ...