HYB18T1G160BFL QIMONDA [Qimonda AG], HYB18T1G160BFL Datasheet
HYB18T1G160BFL
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HYB18T1G160BFL Summary of contents
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HYS64T128020EML-3S-B HYS64T128020EML-3.7-B Revision History: 2007-05, Rev. 0.5 Page Subjects (major changes since last revision) We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to ...
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... Features List of Micro-DIMM features • 214-Pin PC-5300,PC2-4200 and PC2-3200 DDR2 SDRAM memory modules for use as main memory when installed in systems such as mobile personal computers. • 128M × 64 module organisation and 64M ×16 chip organisation • JEDEC standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V (± ...
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... QAG DDR2 SDRAM Component Ranks SDRAM Raw Part Number Organizatio Card n Nos. 2 x16 A HYB18T1G160BFL 8 4 Preliminary Internet Data Sheet HYS64T128020EML-[3S/3.7/5]-B 2 PROM 2 C protocol. The first 128 bytes are TABLE 2 Ordering Information Description SDRAM ...
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... Note: When sampled at the cross point of the rising edge of CK,and SSTL falling edge of CK, RAS, CAS and WE define the operation to be executed by the SDRAM. SSTL Bank Address Bus 1:0 Note: Select internal SDRAM memory bank SSTL 5 Preliminary Internet Data Sheet HYS64T128020EML-[3S/3.7/5]-B (214 pins). The abbreviations used in Figure 1 ...
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Ball No. Name Pin Type 46 BA2 161 A0 I 159 158 157 155 A8 I 154 A9 I ...
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Ball No. Name Pin Type 125 DQ14 I/O 126 DQ15 I/O 24 DQ16 I/O 25 DQ17 I/O 30 DQ18 I/O 31 DQ19 I/O 128 DQ20 I/O 129 DQ21 I/O 133 DQ22 I/O 134 DQ23 I/O 33 DQ24 I/O 34 DQ25 ...
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Ball No. Name Pin Type 200 DQ54 I/O 201 DQ55 I/O 95 DQ56 I/O 96 DQ57 I/O 101 DQ58 I/O 102 DQ59 I/O 203 DQ60 I/O 204 DQ61 I/O 208 DQ62 I/O 209 DQ63 I/O 7 DQS0 I/O 6 DQS0 ...
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Ball No. Name Pin Type 211 SA0 I 213 SA1 I Power Supplies REF V 42, 45, 49, 53, PWR DD 57, 61, 64, 146, 149, 152, 156, 160, 164, 168, 171 V 107 PWR DDSPD V ...
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Enables the associated DDR2 SDRAM command decoder when LOW and disables the command decoder when HIGH. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is ...
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Pin Configuration for Two-Piece Mezzanine Socket on MDIMM (214 pins) Rev. 0.5, 2007-05 05212007-7F24-MITO Preliminary Internet Data Sheet HYS64T128020EML-[3S/3.7/5]-B Unbuffered DDR2 SDRAM MicroDIMM Modules 11 FIGURE 1 ...
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Electrical Characteristics This chapter lists the electrical characteristics. 3.1 Absolute Maximum Ratings Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Symbol Parameter V V Voltage on pin relative ...
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Parameter Symbol V Device Supply Voltage DD V Output Supply Voltage DDQ V Input Reference Voltage REF V SPD Supply Voltage DDSPD V DC Input Logic High IH(DC Input Logic Low IL ( Output Leakage ...
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AC Characteristics This chapter describes the AC characteristics. 3.3.1 Speed Grade Definitions This chapter contains the Speed Grade Definition tables. Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ ...
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Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter RAS-CAS-Delay Row Precharge Time 1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential ...
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AC Timing Parameters This chapter contains the AC Timing Parameters Parameter DQ output access time from CAS to CAS command delay Average clock high pulse width Average clock period CKE minimum pulse width ( high and ...
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Parameter DQ hold skew factor Read preamble Read postamble Active to active command period for 1KB page size products Active to active command period for 2KB page size products Internal Read to Precharge command delay Write preamble Write postamble Write ...
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DAL = WR + RU{ (ns) / (ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For the division is not already an integer, round up ...
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WTR CK Rev. 0.5, 2007-05 05212007-7F24-MITO Preliminary Internet Data Sheet HYS64T128020EML-[3S/3.7/5]-B Unbuffered DDR2 SDRAM MicroDIMM Modules Method for calculating transitions and endpoint Differential input waveform ...
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Parameter DQ output access time from CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks ...
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Parameter Data hold skew factor Average periodic refresh Interval Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Precharge-All (8 banks) command period Read preamble Read postamble Active bank A to Active bank B command ...
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MIN ( , ) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can greater than the minimum specification ...
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Parameter DQ and DM input setup time (single ended data strobe) DQS falling edge hold time from CK (write cycle) DQS falling edge to CK setup time (write cycle) Four Activate Window period Four Activate Window period Clock half period ...
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Parameter Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command Exit Self-Refresh to Read command Write recovery time for write with Auto- Precharge 1) For details and notes see the relevant Qimonda ...
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ODT AC Electrical Characteristics This chapter describes the ODT AC electrical characteristics. ODT AC Characteristics and Operating Conditions for DDR2-667& DDR2-800 Symbol Parameter / Condition t ODT turn-on delay AOND t ODT turn-on AON t ODT turn-on (Power-Down Modes) ...
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ODT AC Characteristics and Operating Conditions for DDR2-533 & DDR2-400 Symbol Parameter / Condition t ODT turn-on delay AOND t ODT turn-on AON t ODT turn-on (Power-Down Modes) AONPD t ODT turn-off delay AOFD t ODT turn-off AOF t ODT ...
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I 3.4 Specifications and Conditions DD This chapter describes the I Specifications and Conditions. DD Parameter Operating Current One bank Active - Precharge CK.MIN valid commands. Address and control inputs are SWITCHING, Databus inputs are ...
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Parameter Self-Refresh Current CKE ≤ 0.2 V; external clock off, CK and Other control and address inputs are FLOATING, Data I bus inputs are FLOATING. current values are guaranteed up to DD6 All Bank Interleave Read ...
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Product Type HYS64T128020EML-3S-B Organization 1GB 2 Ranks x64 -3S Symbol I 588 DD0 I 628 DD1 I 96 DD2P I 520 DD2N I 480 DD2Q I 360 DD3P( MRS = 0) I 120 DD3P( MRS = 1) I 560 DD3N ...
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... Table 22 “SPD Codes for HYS64T128020EML-[3S/3.7/5]-B” on Page 30 Product Type Organization Label Code JEDEC SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 Number of Column Addresses 5 DIMM Rank and Stacking Information 6 Data Width 7 Not used 8 ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description 15 Not used 16 Burst Length Supported 17 Number of Banks on SDRAM Device 18 Supported CAS Latencies 19 DIMM Mechanical Characteristics 20 DIMM Type Information 21 DIMM Attributes 22 ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description t 41 [ns] RC.MIN t 42 [ns] RFC.MIN t 43 [ns] CK.MAX t 44 [ns] DQSQ.MAX t 45 [ns] QHS.MAX 46 PLL Relock Time Delta / ∆ ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description 67 Manufacturer’s JEDEC ID Code (4) 68 Manufacturer’s JEDEC ID Code (5) 69 Manufacturer’s JEDEC ID Code (6) 70 Manufacturer’s JEDEC ID Code (7) 71 Manufacturer’s JEDEC ID Code (8) ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description 93 Module Manufacturing Date Year 94 Module Manufacturing Date Week Module Serial Number 99 - 127 Not used 128 - Blank for customer use 255 Rev. 0.5, ...
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Package Outlines This chaper contains the package outlines of the products. Notes 1. General tolerances +/- 0.15 2. Drawing according to ISO 8015 Rev. 0.5, 2007-05 05212007-7F24-MITO Preliminary Internet Data Sheet HYS64T128020EML-[3S/3.7/5]-B Unbuffered DDR2 SDRAM MicroDIMM Modules Package Outline ...
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... Micro-DIMM HYS 64 DDR2 DRAM HYB 18 Field Description 1 Qimonda Module Prefix 2 Module Data Width [bit] 3 DRAM Technology 4 Memory Density per I/O [Mbit]; 1) Module Density 5 Raw Card Generation 6 Number of Module Ranks 7 Product Variations 8 Package, Lead-Free Status 9 Module Type Rev. 0.5, 2007-05 05212007-7F24-MITO Unbuffered DDR2 SDRAM MicroDIMM Modules ...
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... Field Description 10 Speed Grade 11 Die Revision 1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column “Coding”. Field Description 1 Qimonda Component Prefix ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Edition 2007-05 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 München, Germany © Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or ...