HYB18T1G400AF QIMONDA [Qimonda AG], HYB18T1G400AF Datasheet
HYB18T1G400AF
Related parts for HYB18T1G400AF
HYB18T1G400AF Summary of contents
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HYS72T128001HR–5–A, HYS72T256000HR–[3S/3.7/5]–A Revision History: 2007-02, Rev. 1.4 Page Subjects (major changes since last revision) All Adapted internet edition All Added HYS72T256000HR-3S-A: Updated Ordering Information, Block Diagrams, Previous Revision: Rev. 1.31, 2006-09 All Qimonda Update Previous Revision: Rev. 1.3, 2006-01 Added ...
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... Features • 240-Pin PC2–4200 and PC2–3200 DDR2 SDRAM memory modules for PC, Workstation and Server main memory applications. • One rank 128M ×72, 256M ×72 module organization and 128M x 8, 256M ×4 chip organization • Standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V (± ...
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... DDR2 technology. DIMMs are available as ECC modules in 128M ×72 (1 GByte) and 256M ×72 (2 GByte) organization and density, intended for mounting into 240-Pin connector sockets. The memory array is designed with 1-Gbit Double-Data-Rate- Two (DDR2) Synchronous DRAMs. All control and address 1) Product Type Compliance Code PC2– ...
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... Product Type DRAM Components HYS72T128001HR HYB18T1G800AF HYS72T256000HR HYB18T1G400AF 1) Green Product 2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet. Rev. 1.4, 2007-02 03062006-GD6J-14FP HYS72T[128/256]00xHR–[3S/3.7/5]–A Registered DDR2 SDRAM Modules 1) DRAM Density DRAM Organisation 128M ×8 1 Gbit 256M × ...
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Pin Configuration 2.1 Pin Configuration The pin configuration of the Registered DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The abbreviations used in columns Pin and Buffer Type are explained in Ball No. Name Pin ...
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Ball No. Name Pin Type 188 A0 I 183 182 180 179 A8 I 177 A10 ...
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Ball No. Name Pin Type Data Signals 3 DQ0 I/O 4 DQ1 I/O 9 DQ2 I/O 10 DQ3 I/O 122 DQ4 I/O 123 DQ5 I/O 128 DQ6 I/O 129 DQ7 I/O 12 DQ8 I/O 13 DQ9 I/O 21 DQ10 I/O ...
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Ball No. Name Pin Type 206 DQ39 I/O 89 DQ40 I/O 90 DQ41 I/O 95 DQ42 I/O 96 DQ43 I/O 208 DQ44 I/O 209 DQ45 I/O 214 DQ46 I/O 215 DQ47 I/O 98 DQ48 I/O 99 DQ49 I/O 107 DQ50 ...
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Ball No. Name Pin Type Data Strobe Bus 7 DQS0 I/O 6 DQS0 I/O 16 DQS1 I/O 15 DQS1 I/O 28 DQS2 I/O 27 DQS2 I/O 37 DQS3 I/O 36 DQS3 I/O 84 DQS4 I/O 83 DQS4 I/O 93 DQS5 ...
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Ball No. Name Pin Type Data Mask 125 DM0 I 134 DM1 I 146 DM2 I 155 DM3 I 202 DM4 I 211 DM5 I 223 DM6 I 232 DM7 I 164 DM8 I EEPROM 120 SCL I 119 SDA ...
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Ball No. Name Pin Type Other Pins 19, 55, 68, 102 137, 138, 173, 220, 221 195 ODT0 I 77 ODT1 Abbreviation SSTL CMOS OD Abbreviation I O I/O AI PWR GND NU NC Rev. ...
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Rev. 1.4, 2007-02 03062006-GD6J-14FP HYS72T[128/256]00xHR–[3S/3.7/5]–A Registered DDR2 SDRAM Modules Pin Configuration for RDIMM (240 pins) 13 Internet Data Sheet FIGURE 1 ...
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Electrical Characteristics 3.1 Absolute Maximum Ratings Parameter V Voltage on any pins relative Voltage on relative Voltage on relative to DDQ SS Storage Humidity (without condensation) Attention: Stresses above the ...
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DC Operating Conditions Parameter DIMM Module Operating Temperature Range (ambient) DRAM Component Case Temperature Range Storage Temperature Barometric Pressure (operating & storage) Operating Humidity (relative) 1) When operating this product in the 85 ° °C setting EMR(2) ...
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AC Characteristics 3.3.1 Speed Grades Definitions Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Symbol t Clock Frequency @ Row Active Time ...
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Parameter CKE minimum pulse width ( high and low pulse width) Average clock low pulse width Auto-Precharge write recovery + precharge time Minimum time clocks remain ON after CKE asynchronously drops LOW DQ and DM input hold time DQ and ...
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Parameter Exit precharge power-down to any valid command (other than NOP or Deselect) Exit self-refresh to a non-read command Exit self-refresh to read command Write command to DQS associated clock edges 1) For details and notes see the relevant Qimonda ...
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used in conjunction with t to derive the DRAM output timing QHS following equation; = MIN ( , HP ...
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Rev. 1.4, 2007-02 03062006-GD6J-14FP HYS72T[128/256]00xHR–[3S/3.7/5]–A Registered DDR2 SDRAM Modules Differential input waveform timing - Differential input waveform timing - 20 Internet Data Sheet FIGURE and DS DS FIGURE and lS lH ...
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Parameter DQ output access time from CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks ...
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Parameter Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Precharge-All (8 banks) command period Read preamble Read postamble Active bank A to Active bank B command period Active bank A to Active bank B ...
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The , and , parameters are referenced to a specific voltage level, which specify when the device output is no longer driving HZ RPST LZ RPRE begins ...
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Parameter DQS falling edge hold time from CK (write cycle) DQS falling edge to CK setup time (write cycle) Clock half period Data-out high-impedance time from Address and control input hold time Address and control input pulse ...
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Parameter Exit Self-Refresh to Read command Write recovery time for write with Auto- Precharge 1) For details and notes see the relevant Qimonda component data sheet 1.8 V ± 0 1.8 V ±0.1 V. See ...
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ODT AC Electrical Characteristics Symbol Parameter / Condition t ODT turn-on delay AOND t ODT turn-on AON t ODT turn-on (Power-Down Modes) AONPD t ODT turn-off delay AOFD t ODT turn-off AOF t ODT turn-off (Power-Down Modes) AOFPD t ...
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ODT AC Characteristics and Operating Conditions for DDR2-533 & DDR2-400 Symbol Parameter / Condition t ODT turn-on delay AOND t ODT turn-on AON t ODT turn-on (Power-Down Modes) AONPD t ODT turn-off delay AOFD t ODT turn-off AOF t ODT ...
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Parameter Active Standby Current Burst Read: All banks open; Continuous burst reads CKE is HIGH HIGH between valid commands. Address inputs ...
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Product Type Organization 2 GByte 1 Rank ×72 –3S Symbol Max. I 2130 DD0 I 2490 DD1 I 1680 DD2N I 720 DD2P I 1320 DD2Q I 1770 DD3N I 470 DD3P.MRS=0 I 720 DD3P.MRS=1 I 4200 DD4R I 4200 ...
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... Table 20 “HYS72T[128/256]00xHR-[3S/3.7/5]-A” on Page 30 Product Type Organization Label Code JEDEC SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 Number of Column Addresses 5 DIMM Rank and Stacking Information 6 Data Width 7 Not used 8 Interface Voltage Level ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description 14 Error Checking SDRAM Width 15 Not used 16 Burst Length Supported 17 Number of Banks on SDRAM Device 18 Supported CAS Latencies 19 DIMM Mechanical Characteristics 20 DIMM Type ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description and Extension RC RFC t 41 [ns] RC.MIN t 42 [ns] RFC.MIN t 43 [ns] CK.MAX t 44 [ns] DQSQ.MAX t 45 [ns] QHS.MAX 46 PLL Relock ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description 66 Manufacturer’s JEDEC ID Code (3) 67 Manufacturer’s JEDEC ID Code (4) 68 Manufacturer’s JEDEC ID Code (5) 69 Manufacturer’s JEDEC ID Code (6) 70 Manufacturer’s JEDEC ID Code (7) ...
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Product Type Organization Label Code JEDEC SPD Revision Byte# Description 92 Test Program Revision Code 93 Module Manufacturing Date Year 94 Module Manufacturing Date Week Module Serial Number 99 - 127 Not used 128 - Blank for ...
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Package Outlines Rev. 1.4, 2007-02 03062006-GD6J-14FP HYS72T[128/256]00xHR–[3S/3.7/5]–A Registered DDR2 SDRAM Modules Package Outline Raw Card A L-DIM-240-11 35 Internet Data Sheet FIGURE 5 ...
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Rev. 1.4, 2007-02 03062006-GD6J-14FP HYS72T[128/256]00xHR–[3S/3.7/5]–A Registered DDR2 SDRAM Modules Package Outline Raw Card C L-DIM-240-13 36 Internet Data Sheet FIGURE 6 ...
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... Micro-DIMM HYS 64 DDR2 DRAM HYB 18 Field Description 1 Qimonda Module Prefix 2 Module Data Width [bit] 3 DRAM Technology 4 Memory Density per I/O [Mbit]; 1) Module Density 5 Raw Card Generation 6 Number of Module Ranks 7 Product Variations 8 Package, Lead-Free Status 9 Module Type Rev. 1.4, 2007-02 03062006-GD6J-14FP field number. The detailed field description together with ...
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... Field Description 10 Speed Grade 11 Die Revision 1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column “Coding”. Field Description 1 Qimonda Component Prefix ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Edition 2007-02 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 München, Germany © Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or ...