AT45DB041-CC ATMEL [ATMEL Corporation], AT45DB041-CC Datasheet - Page 2

• Manufacturer Part Number: AT45DB041-CC
• Description: 4-Megabit 2.7-volt Only Serial DataFlash
• Manufacturer: ATMEL [ATMEL Corporation]

noise, and reduces package size and active pin count. The
device is optimized for use in many commercial and indus-
trial applications where high density, low pin count, low
voltage, and low power are essential. Typical applications
for the DataFlash are digital voice storage, image storage,
and data storage. The device operates at clock frequencies
up to 5 MHz with a typical active read current consumption
of 4 mA.
To allow for simple in-system reprogrammability, the
AT45DB041 does not require high input voltages for pro-
Block Diagram
Device Operation
The device operation is controlled by instructions from the
host processor. The list of instructions and their associated
opcodes are contained in Table 1 and Table 2. A valid
instruction starts with the falling edge of CS followed by the
appropriate 8-bit opcode and the desired buffer or main
memory address location. While the CS pin is low, toggling
the SCK pin controls the loading of the opcode and the
desired buffer or main memory address location through
the SI (serial input) pin. All instructions, addresses, and
data are transferred with the most significant bit (MSB) first.
Read
By specifying the appropriate opcode, data can be read
from the main memory or from either one of the two data
buffers.
MAIN MEMORY PAGE READ: A main memory read allows
the user to read data directly from any one of the 2048
pages in the main memory, bypassing both of the data buff-
ers and leaving the contents of the buffers unchanged. To
start a page read, the 8-bit opcode, 52H, is followed by 24
address bits and 32 don’t care bits. In the AT45DB041, the
first four address bits are reserved for larger density
devices (see Notes on page 8), the next 11 address bits
2
RDY/BUSY
AT45DB041
RESET
GND
SCK
V
WP
CS
CC
PAGE (264 BYTES)
BUFFER 1 (264 BYTES)
SI
FLASH MEMORY ARRAY
I/O INTERFACE
gramming. The device operates from a single power sup-
p ly , 2. 7V to 3. 6V , f o r b o th t he pr o g r am an d r e a d
operations. The AT45DB041 is enabled through the chip
select pin (CS) and accessed via a three-wire interface
consisting of the Serial Input (SI), Serial Output (SO), and
the Serial Clock (SCK).
All programming cycles are self-timed, and no separate
erase cycle is required before programming.
(PA10-PA0) specify the page address, and the next nine
address bits (BA8-BA0) specify the starting byte address
within the page. The 32 don’t care bits which follow the 24
address bits are sent to initialize the read operation. Fol-
lowing the 32 don’t care bits, additional pulses on SCK
result in serial data being output on the SO (serial output)
pin. The CS pin must remain low during the loading of the
opcode, the address bits, and the reading of data. When
the end of a page in main memory is reached during a main
memory page read, the device will continue reading at the
beginning of the same page. A low to high transition on the
CS pin will terminate the read operation and tri-state the
SO pin.
BUFFER READ: Data can be read from either one of the
two buffers, using different opcodes to specify which buffer
to read from. An opcode of 54H is used to read data from
buffer 1, and an opcode of 56H is used to read data from
buffer 2. To perform a buffer read, the eight bits of the
opcode must be followed by 15 don’t care bits, nine
address bits, and eight don't care bits. Since the buffer size
is 264-bytes, nine address bits (BFA8-BFA0) are required
to specify the first byte of data to be read from the buffer.
BUFFER 2 (264 BYTES)
SO