AT45DB081B-CU ATMEL [ATMEL Corporation], AT45DB081B-CU Datasheet

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... Green (Pb/Halide-free) Packaging Options Description The AT45DB081B is a 2.5-volt or 2.7-volt only, serial interface Flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. Its 8,650,752 bits of memory are organized as 4096 pages of 264 bytes each. In addition to the main memory, the AT45DB081B also contains two SRAM data buffers of 264 bytes each ...

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... VCC GND RDY/BUSY To provide optimal flexibility, the memory array of the AT45DB081B is divided into three levels of granularity comprising of sectors, blocks, and pages. The Memory Architecture Diagram illustrates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page-by-page basis ...

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... Continuous Array Read command can be utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional addressing information or control signals need to be provided. The DataFlash incorporates an internal address counter that will automatically increment on every clock AT45DB081B PAGE ARCHITECTURE 8 Pages PAGE 0 ...

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... AT45DB081B 4 cycle, allowing one continuous read operation without the need of additional address sequences. To perform a continuous read, an opcode of 68H or E8H must be clocked into the device followed by 24 address bits and 32 don’t care bits. The first three bits of the 24-bit address sequence are reserved for upward and downward compatibility to larger and smaller density devices (see Notes under “ ...

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... The device density is indicated using bits and 2 of the status register. For the AT45DB081B, the four bits are and 1. The decimal value of these four binary bits does not equate to the device density; the three bits represent a combinational code relating to differing densities of Serial DataFlash devices, allowing a total of sixteen dif- ferent density configurations ...

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... AT45DB081B 6 BUFFER TO MAIN MEMORY PAGE PROGRAM WITHOUT BUILT-IN ERASE: A previously erased page within main memory can be programmed with the contents of either buffer 1 or buffer 2. To start the operation, an 8-bit opcode, 88H for buffer 1 or 89H for buffer 2, must be followed by the three reserved bits, 12 address bits (PA11 - PA0) that specify the page in the main memory to be written, and nine addi- tional don’ ...

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... The operation is inter- nally self-timed and should take place in a maximum time of t status register will indicate that the part is busy. AT45DB081B . During EP ), the status XFR ...

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... Operation Mode Summary Pin Descriptions AT45DB081B sector is programmed or reprogrammed sequentially page-by-page, then the pro- gramming algorithm shown in Figure 1 on page 26 is recommended. Otherwise, if multiple bytes in a page or several pages are programmed randomly in a sector, then the programming algorithm shown in Figure 2 on page 27 is recommended. Each page within a sector must be updated/rewritten at least once within every 10,000 cumulative page erase/program operations in that sector ...

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... CS pin will be required to start a valid instruc- tion. The SPI mode will be automatically selected on every falling edge sampling the inactive clock state. After power is applied and V datasheet value, the system should wait 20 ms before an operational mode is started. AT45DB081B is at the minimum CC 9 ...

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... Auto Page Rewrite through Buffer 2 Note: In Tables 2 and 3, an SCK mode designation of “Any” denotes any one of the four modes of operation (Inactive Clock Polarity Low, Inactive Clock Polarity High, SPI Mode 0, or SPI Mode 3). AT45DB081B 10 SCK Mode Inactive Clock Polarity Low or High ...

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... N/A N AT45DB081B Address Byte ...

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... Output High Voltage OH Note during a buffer read is 20mA maximum. cc1 AT45DB081B 12 *NOTICE: + 0.6V CC AT45DB081B (2.5V Version – 2. the minimum specified datasheet value, the system should wait 20 ms before an opera- CC Condition CS, RESET all inputs CC at CMOS levels MHz ...

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... Page Programming Time P t Page Erase Time PE t Block Erase Time BE t RESET Pulse Width RST t RESET Recovery Time REC 2225I–DFLSH–9/05 AT45DB081B AT45DB081B (2.5V Version) AT45DB081B Min Max Min Max 250 250 250 250 250 250 ...

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... AC Waveforms Waveform 1 – Inactive Clock Polarity Low and SPI Mode 0 CS SCK HIGH IMPEDANCE SO SI Waveform 2 – Inactive Clock Polarity High and SPI Mode CSS SCK HIGH AT45DB081B 14 2.4V AC 2.0 DRIVING 0.8 LEVELS 0.45V < (10 DEVICE UNDER ...

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... For densities larger than 8M bits, the “r” bits become the most significant Page Address bit for the appropriate density. 2225I–DFLSH–9/05 SI CMD 8 bits 8 bits Page Address (PA11-PA0) (BA8-BA0/BFA8-BFA0) AT45DB081B t t REC CSS t RST HIGH IMPEDANCE 8 bits LSB Byte/Buffer Address ...

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... CMD Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page Each transition represents 8 bits and 8 clock cycles AT45DB081B 16 The following block diagram and waveforms illustrate the various write sequences available. FLASH MEMORY ARRAY PAGE PROGRAM THROUGH BUFFER 2 ...

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... MAIN MEMORY PAGE READ I/O INTERFACE SO PA6-0, BA8 BA7-0 X Starts reading page data into buffer CMD PA11-7 PA6-0, X CMD X X···X, BFA8 BFA7-0 AT45DB081B MAIN MEMORY PAGE TO BUFFER 2 BUFFER 2 (264 BYTES) BUFFER 2 READ n 1st byte read ...

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... Detailed Bit-level Read Timing – Inactive Clock Polarity Low Continuous Array Read (Opcode: 68H) CS SCK HIGH-IMPEDANCE SO Main Memory Page Read (Opcode: 52H) CS SCK COMMAND OPCODE AT45DB081B DATA OUT ...

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... HIGH-IMPEDANCE SO 2225I–DFLSH–9/ HIGH-IMPEDANCE AT45DB081B DATA OUT MSB STATUS REGISTER OUTPUT MSB ...

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... Detailed Bit-level Read Timing – Inactive Clock Polarity High Continuous Array Read (Opcode: 68H) CS SCK HIGH-IMPEDANCE SO Main Memory Page Read (Opcode: 52H) CS SCK COMMAND OPCODE AT45DB081B DATA OUT HIGH-IMPEDANCE ...

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... COMMAND OPCODE HIGH-IMPEDANCE SO 2225I–DFLSH–9/ HIGH-IMPEDANCE AT45DB081B DATA OUT MSB STATUS REGISTER OUTPUT MSB LSB ...

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... Detailed Bit-level Read Timing – SPI Mode 0 Continuous Array Read (Opcode: E8H) CS SCK HIGH-IMPEDANCE SO Main Memory Page Read (Opcode: D2H) CS SCK COMMAND OPCODE AT45DB081B DATA OUT ...

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... HIGH-IMPEDANCE SO 2225I–DFLSH–9/ HIGH-IMPEDANCE AT45DB081B DATA OUT MSB STATUS REGISTER OUTPUT MSB D 4 ...

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... Detailed Bit-level Read Timing – SPI Mode 3 Continuous Array Read (Opcode: E8H) CS SCK HIGH-IMPEDANCE SO Main Memory Page Read (Opcode: D2H) CS SCK COMMAND OPCODE AT45DB081B DATA OUT HIGH-IMPEDANCE ...

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... COMMAND OPCODE HIGH-IMPEDANCE SO 2225I–DFLSH–9/ HIGH-IMPEDANCE AT45DB081B DATA OUT MSB STATUS REGISTER OUTPUT MSB LSB ...

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... A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer to Main Memory Page Program operation. 3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. AT45DB081B 26 START provide address ...

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... X • • • • • • • • • AT45DB081B If planning to modify multiple bytes currently stored within a page of the Flash array PA5 PA4 PA3 PA2 - PA0 • • • ...

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... Ordering Code AT45DB081B-CC AT45DB081B-CNC AT45DB081B-RC AT45DB081B-TC AT45DB081B-CI AT45DB081B-CNI AT45DB081B-RI AT45DB081B-TI AT45DB081B-CC-2.5 AT45DB081B-CNC-2.5 AT45DB081B-RC-2.5 AT45DB081B-TC-2.5 Ordering Code AT45DB081B-CNU AT45DB081B-RU AT45DB081B-TU AT45DB081B-CU Package Type Package Operation Range 14C1 Commercial 8CN3 ( 28R 28T 14C1 Industrial 8CN3 (- 28R 28T 14C1 Commercial ...

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... MAX 2.0 (0.079 4.0 (0.157 0.46 (0.018) 1.00 (0.0394) BSC DIA BALL TYP BOTTOM VIEW TITLE 14C1, 14-ball ( Array), 4 1.4 mm Body, 1.0 mm Ball Pitch Chip-scale Ball Grid Array Package (CBGA) AT45DB081B SIDE VIEW 0.30 (0.012)MIN 1.50 (0.059) REF DRAWING NO. 04/11/01 REV. 14C1 A 29 ...

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... All dimensions and tolerance conform to ASME Y 14.5M, 1994. 2. The surface finish of the package shall be EDM Charmille #24-27. 3. Unless otherwise specified tolerance: Decimal ±0.05, Angular ±2 4. Metal Pad Dimensions. 2325 Orchard Parkway San Jose, CA 95131 R AT45DB081B 30 D Top View Side View Pin1 Pad Corner L1 ...

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... Mold Flash or protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R 2225I–DFLSH–9/ TITLE 28R, 28-lead, 0.330" Body Width, Plastic Gull Wing Small Outline (SOIC) AT45DB081B COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A 2.39 – 2.79 A1 0.050 – 0.356 D 18 ...

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... This package conforms to JEDEC reference MO-183. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion 0.15 mm per side and 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT45DB081B 32 PIN SEATING PLANE ...

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... Atmel Corporation 2005. All rights reserved. Atmel registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 ...