HYB18T512800BF QIMONDA [Qimonda AG], HYB18T512800BF Datasheet - Page 19

• Manufacturer Part Number: HYB18T512800BF
• Description: 240-Pin Registered DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

1) For details and notes see the relevant Qimonda component data sheet
2)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
6) Inputs are not recognized as valid until
7) The output timing reference voltage level is
8) New units, ‘
9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to
11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and
12)
13) DAL = WR + RU{
14)
15) Input waveform timing
16)
Rev. 1.1, 2007-03
03292006-EO3M-LEK7
Parameter
Read postamble
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time
Internal write to read command delay
Exit power down to read command
Exit active power-down mode to read command
(slow exit, lower power)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit self-refresh to a non-read command
Exit self-refresh to read command
Write command to DQS associated clock edges
V
and then restarted through the specified initialization sequence before normal operation can continue.
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
input reference level is the crosspoint when in differential strobe mode.
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
ps and
t
= - 900 ps – 293 ps = – 1193 ps and
DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations).
t
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of
of the division is not already an integer, round up to the next highest integer.
DDR2–533 at
t
the input signal crossing at the
at the
V
t
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
DQSCK.MAX(DERATED)
CKE.MIN
DAL.nCK
DQSQ
DDQ
IH.DC.MIN
: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
= 1.8 V ± 0.1V;
V
t
of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
= WR [nCK] +
IL.DC
ERR(6- 10PER).MAX
. See
t
CK.AVG
level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between
t
CK
t
Figure
CK
‘ is used for both concepts. Example:
t
RP
= 3.75 ns with
t
‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘
=
IS
(ns) /
t
+ 2 x
V
DQSCK.MAX
t
3.
DD
t
nRP.nCK
= + 293 ps, then
DH
= 1.8 V ± 0.1 V.
t
CK
with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
t
CK
(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For
+
= WR + RU{
–
V
t
t
IH
IH.DC
t
WR
ERR(6-10PER).MIN
.
programmed to 4 clocks.
t
level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
LZ.DQ.MAX(DERATED)
V
t
REF
DQSCK.MIN(DERATED)
t
RP
V
stabilizes. During the period before
TT
[ps] /
.
= 400 ps + 272 ps = + 672 ps. Similarly,
t
CK.AVG
t
Symbol
t
t
t
t
t
t
t
t
t
t
t
WL
XP
RPST
RTP
WPRE
WPST
WR
WTR
XARD
XARDS
XP
XSNR
XSRD
= 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
= 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
t
[ps] }, where WR is the value programmed in the EMR.
CK.AVG
=
t
DQSCK.MIN
t
DAL
+
19
= 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
t
ERR.2PER(Min)
–
DDR2–800
0.4
7.5
0.35
0.4
15
7.5
2
8 – AL
2
t
200
RL – 1
Min.
t
RFC
ERR(6-10PER).MAX
HYS72T[64/128/256]xxxHP–[25F/2.5/3/3S/3.7]–B
t
+10
CK
.
V
refers to the application clock period. Example: For
REF
t
CK.AVG
stabilizes, CKE = 0.2 x
t
‘ represents the actual
= – 400 ps – 293 ps = – 693 ps and
LZ.DQ
0.6
—
—
0.6
—
—
—
—
—
—
Max.
—
240-Pin Registered DDR2 SDRAM
for DDR2–667 derates to
t
ERR(6-10per)
V
Unit
t
ns
t
t
ns
ns
nCK
nCK
nCK
ns
nCK
nCK
CK.AVG
CK.AVG
CK.AVG
DDQ
of the input clock. (output
t
Internet Data Sheet
CK.AVG
t
is recognized as low.
ERR(6-10PER).MIN
V
IL.DC.MAX
of the input clock
Note
8)
28)30)
31)
—
—
31)
31)32)
—
—
—
31)
—
—
t
LZ.DQ.MIN(DERATED)
t
RP
, if the result
1)2)3)4)5)6)7)
and
= – 272