HM6-6642-9 INTERSIL [Intersil Corporation], HM6-6642-9 Datasheet - Page 7

• Manufacturer Part Number: HM6-6642-9
• Description: 512 x 8 CMOS PROM
• Manufacturer: INTERSIL [Intersil Corporation]

Capacitance
NOTES:
Switching Waveform
NOTE: G has the same timing as G except signal is inverted.
Test Load Circuit
1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate
2. Tested at initial design and after major design changes.
3. Typical derating 5mA/MHz increase in ICCOP.
4. V
SYMBOL
equivalent C
CO
CI
CC
= 4.5V and 5.5V.
Input Capacitance (Note 2)
Output Capacitance (Note 2)
REFERENCE
L
= 50pF (min) - for C
T
A
(NOTE)
= +25
TIME
PARAMETER
A
Q
G
E
NOTE:
TEST HEAD
CAPACITANCE,
INCLUDES STRAY
AND JIG CAPACITANCE
o
C
TGXQZ
(5)
DUT
L
TAVEL
(NOTE)
greater than 50pF, access time is derated by 0.15ns per pF.
(9)
C
TEHEL
L
(8)
-1
MIN
-
-
ADD VALID
0
FIGURE 3. READ CYCLE
LIMITS
TELAX
TGVQX
TAVQV
(10)
(2)
HM-6642
TELQV
(4)
(1)
TGVQV
MAX
10.0
12.0
(3)
6-7
1
TELEH
IOH
EQUIVALENT CIRCUIT
(6)
UNITS
TELEL (7)
pF
pF
2
DATA VALID
TAVEL (9)
f = 1MHz, All Measurements Reference Device
Ground
1.5V
3
TEHEL (8)
TEST CONDITIONS
IOL
NEXT ADD
4 5 6
TGXQZ (5)