STK14CA8-N25I ETC [List of Unclassifed Manufacturers], STK14CA8-N25I Datasheet - Page 13

• Manufacturer Part Number: STK14CA8-N25I
• Description: 128K x 8 AutoStoreTM nvSRAM QuantumTrapTM CMOS Nonvolatile Static RAM
• Manufacturer: ETC [List of Unclassifed Manufacturers]

Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the
nonvolatile information is transferred into the SRAM
cells. After the t
again be ready for READ and WRITE operations.
The RECALL operation in no way alters the data in
the nonvolatile elements.
PREVENTING AUTOSTORE
The AutoStore™ function can be disabled by initiat-
ing an AutoStore Disable sequence. A sequence of
read operations is performed in a manner similar to
the software STORE initiation. To initiate the
AutoStore Disable sequence, the following sequence
of
The AutoStore™ can be re-enabled by initiating an
AutoStore Enable sequence. A sequence of read
operations is performed in a manner similar to the
software RECALL initiation. To initiate the AutoStore
Enable sequence, the following sequence of
controlled read operations must be performed:
If the AutoStore™ function is disabled or re-enabled
a manual STORE operation (Hardware or Software)
needs to be issued to save the AutoStore state
through subsequent power down cycles. The part
comes from the factory with AutoStore™ enabled.
DATA PROTECTION
The STK14CA8 protects data from corruption during
low-voltage conditions by inhibiting all externally
initiated STORE and WRITE operations. The low-
voltage condition is detected when V
If the STK14CA8 is in a WRITE mode (both
STORE, the WRITE will be inhibited until a negative
transition on
against inadvertent writes during power up or brown
out conditions.
December 2004
W
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6.
E
low
Read address
controlled read operations must be performed:
)
at power-up, after a RECALL, or after a
E
RECALL
or
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
W
cycle time the SRAM will once
is detected. This protects
Valid READ
Valid READ
Valid READ
AutoStore Disable
Valid READ
Valid READ
Valid READ
AutoStore Enable
Valid READ
Valid READ
Valid READ
Valid READ
TM
CC
< V
SWITCH .
E
and
13
E
NOISE CONSIDERATIONS
The STK14CA8 is a high-speed memory and so must
have
approximately 0.1µF connected between V
using leads and traces that are as short as possible.
As with all high-speed CMOS ICs, careful routing of
power, ground and signals will reduce circuit noise.
LOW AVERAGE ACTIVE POWER
CMOS technology provides the STK14CA8 this the
benefit of drawing significantly less current when it is
cycled at times longer than 50ns. Figure 5 shows the
relationship between I
time. Worst-case current consumption is shown for
commercial temperature range, V
enable at maximum frequency. Only standby current
is drawn when the chip is disabled. The overall
average current drawn by the STK14CA8 depends on
the following items:
1. The duty cycle of chip enable.
2. The overall cycle rate for accesses.
3. The ratio of READs to WRITEs.
4. The operating temperature.
5. The V
6. I/O loading.
50
40
30
20
10
0
a
Document Control #ML0022 rev 1.0
high-frequency
CC
Figure 5 Current vs. Cycle time
level.
50
Cycle Time (ns)
CC
100 150 200 300
and READ/WRITE cycle
bypass
CC
= 3.6V, and chip
STK14CA8
Writes
Reads
capacitor
CC
and V
SS
of
,