MT28F320J3FS-12 MICRON [Micron Technology], MT28F320J3FS-12 Datasheet - Page 33
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MT28F320J3FS-12
Manufacturer Part Number
MT28F320J3FS-12
Description
Q-FLASHTM MEMORY
Manufacturer
MICRON [Micron Technology]
Datasheet
1.MT28F320J3FS-12.pdf
(52 pages)
- Current page: 33 of 52
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128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
SET BLOCK LOCK BITS Flowchart
FULL STATUS CHECK PROCEDURE
SET BLOCK LOCK BITS
SET BLOCK LOCK BITs
Read Status Register
Data (see above)
Check if Desired
Block Address
Block Address
Read Status
Full Status
Write 60h,
Write 01h,
Successful
Complete
Register
SR4,5 =
SR3 =
SR7 =
SR4 =
Start
1
0
0
0
Figure 9
0
1
1
1
SET BLOCK LOCK BITS
Command Sequence
Voltage Range Error
Error
Error
33
BUS
OPERATION COMMAND
WRITE
WRITE
READ
STANDBY
BUS
OPERATION COMMAND
STANDBY
STANDBY
STANDBY
Repeat for subsequent lock bit operations.
Full status check can be done after each lock bit set
operation or after a sequence of lock bit set operations
Write FFh after the last lock bit set operation to place
device in read array mode.
SR5, SR4, and SR3 are only cleared by the CLEAR STATUS
REGISTER command in cases where multiple lock bits are set
before full status is checked.
If an error is detected, clear the status register before
attempting retry or other error recovery.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SET BLOCK Data = 60h
LOCK BITS
SETUP
SET BLOCK Data = 01h
LOCK BITS
CONFIRM
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
COMMENTS
Addr = Block Address
Addr = Block Address
Status Register Data
Check SR7
1 = ISM Ready
0 = ISM Busy
COMMENTS
Check SR3
1 = Programming Voltage
Check SR4, SR5
Both 1 = Command
Check SR4
1 = Set Block Lock Bits
Error Detect
Error
Sequence Error
©2002, Micron Technology, Inc.
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