X24C01B ICMIC [IC MICROSYSTEMS], X24C01B Datasheet - Page 10
![no-image](/images/no-image-200.jpg)
X24C01B
Manufacturer Part Number
X24C01B
Description
Serial E2PROM
Manufacturer
ICMIC [IC MICROSYSTEMS]
Datasheet
1.X24C01B.pdf
(14 pages)
X24C01
WRITE CYCLE LIMITS
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
erase/program cycle. During the write cycle, the X24C01
Write Cycle Timing
Notes: (5) Typical values are for T
Guidelines for Calculating Typical Values of
Bus Pull-Up Resistors
Symbol
t
SDA
SCL
WR
(6) t
(6)
time the device requires to automatically complete the internal write operation.
WR
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
120
100
40
20
80
60
0
0
MIN.
RESISTANCE
BUS CAPACITANCE (pF)
Write Cycle Time
20
R
R
WORD n
MAX.
RESISTANCE
MIN
MAX
8th BIT
Parameter
40
=
=
V
A
I
C
OL MIN
60
CC MAX
= 25°C and nominal supply voltage (5V).
BUS
t
R
80100120
=2.6KΟ
ACK
3837 FHD F15
Min.
CONDITION
STOP
10
bus interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its word address.
SYMBOL TABLE
Typ.
WAVEFORM
t
5
WR
(5)
CONDITION
START
INPUTS
Must be
steady
May change
from Low to
High
May change
from High to
Low
Don’t Care:
Changes
Allowed
N/A
Max.
10
ADDRESS
X24C01
OUTPUTS
Will be
steady
Will change
from Low to
High
Will change
from High to
Low
Changing:
State Not
Known
Center Line
is High
Impedance
Units
3837 FHD F05
ms
3837 PGM T08