X24C02B ICMIC [IC MICROSYSTEMS], X24C02B Datasheet - Page 5

• Manufacturer Part Number: X24C02B
• Description: Serial E2PROM
• Manufacturer: ICMIC [IC MICROSYSTEMS]

X24C02
DEVICE ADDRESSING
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave are the device type identifier
Figure 4. Slave Address
The next three significant bits address a particular device.
A system could have up to eight X24C02 devices
bus (see Figure 10). The eight addresses are defined by the
state of the A
The last bit of the slave address defines the operation to be
performed. When set to one a read operation is
selected, when set to zero a write operations is selected.
Figure 5. Byte Write
Figure 6. Page Write
(see Figure 4). For the X24C02 this is fixed as 1010[B].
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24C02
1
DEVICE TYPE
IDENTIFIER
0
, A
0
1
and A
1
A
R
S
T
T
S
2
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24C02
inputs.
ADDRESS
0
SLAVE
A2
ADDRESS
DEVICE
A1
A
C
K
A
R
S
T
T
S
A0
ADDRESS (n)
ADDRESS
WORD
NOTE: In this example n = xxxx 000 (B); x = 1 or 0
R/W
3838 FHD F09
SLAVE
on the
A
C
K
A
C
K
5
DATA n
ADDRESS
WORD
Following the start condition, the X24C02 monitors the
SDA bus comparing the slave address being transmitted
with its slave address (device type and state of A
A
acknowledge on the SDA line. Depending on the state of the
R/W bit, the X24C02 will execute a read or write
WRITE OPERATIONS
Byte Write
For a write operation, the X24C02 requires a second
address field. This address field is the word address,
comprised of eight bits, providing access to any one of the
256 words of memory. Upon receipt of the word
address the X24C02 responds with an acknowledge, and
awaits the next eight bits of data, again responding
with an acknowledge. The master then terminates the
transfer by generating a stop condition, at which time the
X24C02 begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress the
X24C02 inputs are disabled, and the device will not
respond to any requests from the master. Refer to
Figure 5 for the address, acknowledge and data transfer
sequence.
2
inputs). Upon a correct compare the X24C02 outputs an
A
C
K
A
C
K
DATA n+1
DATA
A
C
K
A
C
K
S
T
O
P
P
DATA n+3
3838 FHD F010
3838 FHD F011
operation.
0
A
C
K
, A
O
P
P
S
T
1
and