LT3640EFE LINER [Linear Technology], LT3640EFE Datasheet - Page 12

• Manufacturer Part Number: LT3640EFE
• Description: Dual Monolithic Buck Regulator with Power-On Reset and Watchdog Timer
• Manufacturer: LINER [Linear Technology]

LT3640
APPLICATIONS INFORMATION
Setting the Output Voltages
The internal reference voltage is 1.265V for the high volt-
age channel, and 600mV for the low voltage channel. The
output voltages are set by resistor dividers according to
the following formulas:
Use 1% resistors in the resistor dividers. To avoid noise
problems, R1 should be 100k or less, and R3 should
be 50k or less. Reference designators refer to the Block
Diagram.
Switching Frequency
The LT3640 uses a constant-frequency PWM architecture
that can be programmed to switch from 350kHz to 2.2MHz
by using a resistor tied from the RT pin to ground. Table
1 shows the necessary R
frequency.
Table 1. Switching Frequency vs R
Selection of the operating frequency is mainly a trade-off
between effi ciency and component size. The advantage
of high frequency operation is that smaller inductor and
capacitor values may be used. The disadvantage is lower
effi ciency.
The high switching frequency also decreases the duty
cycle range. The reason is that the LT3640 switches have
fi nite minimum on- and off-times independent of the
switching frequency. The top switch in the high voltage
channel can turn on for a minimum of ~60ns and turn off
for a minimum of ~70ns. The top switch in the low voltage
channel can turn on for a minimum of ~110ns and turn
12
SWITCHING FREQUENCY (MHz)
R
R
2
4
=
=
R
R
1
3
•
•
0.35
0.5
2.2
⎛
⎝ ⎜
⎛
⎝ ⎝ ⎜
1
2
1 265
V
V
0 6
.
OUT
OUT
.
V
2
1
V
−
−
1
⎞
⎠ ⎟
T
1
⎞
⎠ ⎟
value for a desired switching
T
Value
R
82.5
32.4
27.4
267
182
T
(k)
off for a minimum of ~70ns. The minimum and maximum
duty cycles are:
where f
mum switch on-time, and t
off-time. These equations illustrate how duty cycle range
increases when switching frequency decreases.
The internal oscillator of the LT3640 can be synchronized
to an external 350kHz to 2.5MHz positive clock signal on
the SYNC pin. The R
the internal oscillator’s frequency is 20% lower than the
lowest SYNC clock frequency (refer to Table 1). To avoid
erratic operation, the LT3640 ignores the SYNC signal
until the FB1 pin voltage is above 1.165V. When applying
a SYNC signal, the rising edges reset the LT3640’s internal
clock and initiate a switch cycle. The amplitude of the
SYNC signal must be at least 2V. The SYNC pulse width
must be at least 40ns.
V
The LT3640’s minimum operating voltage is 3.6V. A higher
minimum operating voltage can be accurately programmed
with a resistor divider between the V
pin. The EN/UVLO threshold is 1.26V. When the LT3640
is enabled, a 2μA current fl ows out of the EN/UVLO pin
generating hysteresis to prevent the switching action from
falsely disabling the LT3640. Choose the divider resistances
for appropriate hysteresis voltage.
The high voltage nonsynchronous channel operates from
the V
voltage is:
Where V
is the voltage drop of the internal NPN power switch, and
DC
Frequency section). If V
voltage, output will lose regulation.
IN
DC
DC
MAX
V
Voltage Range
IN MIN
IN
MIN
MAX
(
S
is the maximum duty cycle (refer to the Switching
pin. The minimum V
D
is the switching frequency, t
= f
is the forward voltage drop of the catch diode, V
= 1 – f
)
=
S
• t
⎛
⎜
⎝
ON(MIN)
S
V
OUT
• t
DC
OFF(MIN)
T
MAX
1
value should be chosen such that
IN
+
is below the calculated minimum
V
OFF(MIN)
D
IN
⎞
⎟ −
⎠
voltage to regulate output
V
IN
D
is the minimum switch
pin and the EN/UVLO
+
ON(MIN)
V
CE
is the mini-
3640p
CE