BD6088GUL_11 ROHM [Rohm], BD6088GUL_11 Datasheet - Page 11

• Manufacturer Part Number: BD6088GUL_11
• Description: Mulitifunction Backlight LED Driver for Small LCD Panels (Charge Pump Type)
• Manufacturer: ROHM [Rohm]

© 2011 ROHM Co., Ltd. All rights reserved.
www.rohm.com
BD6088GUL
・ Writing protocol
・ Reading protocol
・ Multiple reading protocols
A register address is transferred by the next 1 byte that transferred the slave address and the write-in command. The 3rd
byte writes data in the internal register written in by the 2nd byte, and after 4th byte or, the increment of register address is
carried out automatically. However, when a register address turns into the last address, it is set to 00h by the next
transmission. After the transmission end, the increment of the address is carried out.
It reads from the next byte after writing a slave address and R/W bit. The register to read considers as the following address
accessed at the end, and the data of the address that carried out the increment is read after it. If an address turns into the
last address, the next byte will read out 00h. After the transmission end, the increment of the address is carried out.
After specifying an internal address, it reads by repeated START condition and changing the data transfer direction. The
data of the address that carried out the increment is read after it. If an address turns into the last address, the next byte will
read out 00h. After the transmission end, the increment of the address is carried out.
As for reading protocol and multiple reading protocols, please do A(not acknowledge) after doing the final reading operation.
It stops with read when ending by A(acknowledge), and SDA stops in the state of Low when the readingdata of that time is
0. However, this state returns usually when SCL is moved, data is read, and A(not acknowledge)is done.
S
S
X X X X X X X
X X X X X X X
S
slave address
X X X X X X X
slave address
slave address
from master to slave
from slave to master
from master to slave
from slave to master
from master to slave
from slave to master
R/W=1(read)
R/W=0(write)
R/W=0(write)
D7 D6 D5 D4 D3D2 D1D0
0
1
A
0
A
A7 A6 A5 A4 A3 A2 A1 A0
A
D7 D6 D5 D4 D3 D2 D1 D0
DATA
A7 A6 A5 A4 A3 A2 A1 A0
register address
register address
register address
DATA
increment
A
11/51
register address
A=acknowledge(SDA LOW)
A=not acknowledge(SDA HIGH)
S=START condition
P=STOP condition
increment
A=acknowledge(SDA LOW)
A=not acknowledge(SDA HIGH)
S=START condition
P=STOP condition
*1: Write Timing
A
A=acknowledge(SDA LOW)
A=not acknowledge(SDA HIGH)
S=START condition
P=STOP condition
Sr=repeated START condition
A
D7 D6 D5 D4 D3 D2 D1 D0
A
Sr
D7D6 D5D4D3D2D1D0 A
X X X X X X X
DATA
slave address
DATA
register address
D7 D6 D5 D4 D3 D2 D1 D0
increment
R/W=1(read)
A
DATA
*1
1
register address
A
D7 D6 D5 D4 D3 D2 D1 D0
increment
register address
P
increment
DATA
Technical Note
2011.04 - Rev.A
A
register address
P
increment
A P
*1