ADP3178JR AD [Analog Devices], ADP3178JR Datasheet - Page 8

• Manufacturer Part Number: ADP3178JR
• Description: 4-Bit Programmable Synchronous Buck Controllers
• Manufacturer: AD [Analog Devices]

ADP3158/ADP3178
There are many useful references for quickly designing a power
inductor. Table II gives some examples.
Magnetic Designer Software
Intusoft (http://www.intusoft.com)
Designing Magnetic Components for High-Frequency DC-DC
McLyman, Kg Magnetics
ISBN 1-883107-00-08
Selecting a Standard Inductor
The companies listed in Table III can provide design consul-
tation and deliver power inductors optimized for high power
applications upon request.
Coilcraft
[phone]
http://www.coilcraft.com
Coiltronics
[phone]
http://www.coiltronics.com
Sumida Electric Company
[phone]
http://www.sumida.com
C
The required equivalent series resistance (ESR) and capacitance
drive the selection of the type and quantity of the output capaci-
tors. The ESR must be small enough to contain the voltage
deviation caused by a maximum allowable CPU transient cur-
rent within the specified voltage limits, giving consideration also
to the output ripple and the regulation tolerance. The capaci-
tance must be large enough that the voltage across the capacitor,
which is the sum of the resistive and capacitive voltage deviations,
does not deviate beyond the initial resistive deviation while the
inductor current ramps up or down to the value corresponding
to the new load current. The maximum allowed ESR also repre-
sents the maximum allowed output resistance, R
The cumulative errors in the output voltage regulation cuts into
the available regulation window, V
load regulation this relates directly to the ESR. When consider-
ing dc load regulation, this relates directly to the programmed
output resistance of the power converter.
Some error sources, such as initial voltage accuracy and ripple
voltage, can be directly deducted from the available regulation
window, while other error sources scale proportionally to the
OUT
Converters
Selection—Determining the ESR
Table III. Power Inductor Manufacturers
Table II. Magnetics Design References
WIN
. When considering dynamic
OUT
.
amount of voltage positioning used, which, for an optimal design,
should utilize the maximum that the regulation window will allow.
The error determination is a closed-loop calculation, but it can
be closely approximated. To maintain a conservative design while
avoiding an impractical design, various error sources should
be considered and summed statistically.
The output ripple voltage can be factored into the calculation by
summing the output ripple current with the maximum output
current to determine an effective maximum dynamic current
change. The remaining errors are summed separately according
to the formula:
where k
from the graph of TPC 6, k
current sense resistor, k
the current sense filter components, k
the two termination resistors added at the COMP pin, and k
= 8% accounts for the IC current loop gain tolerance including
the g
The remaining window is then divided by the maximum output
current plus the ripple to determine the maximum allowed ESR
and output resistance:
The output filter capacitor bank must have an ESR of less
than 5 m . One can, for example, use five ZA series capacitors
from Rubycon which would give an ESR of 4.8 m . Without
ADOPT voltage positioning, the ESR would need to be less than
3 m , yielding a 50% increase to eight Rubycon output capacitors.
C
As long as the capacitance of the output capacitor is above a
critical value and the regulating loop is compensated with ADOPT,
the actual value has no influence on the peak-to-peak deviation
of the output voltage to a full step change in the load current.
The critical capacitance can be calculated as follows:
The critical capacitance for the five ZA series Rubycon capaci-
tors is 2.6 mF while the equivalent capacitance is 5 mF. The
capacitance is safely above the critical value.
R
OUT
E MAX
(
1
m
–
—Checking the Capacitance
tolerance.
5
C
I
VID
)
O
m
OUT CRIT
15
I
O
= 0.5% is the initial programmed voltage tolerance
R
I
(
OUT MAX
O
A
1 7
V
.
(
WIN
)
k
RCS
1 5
R
)
.
2
E
(
CSF
V
I
I
H
O
V
O
V
k
= 10% is the summed tolerance of
–
OUT
CSF
WIN
2
RCS
V
I
VID
2 6
O
.
= 2% is the tolerance of the
2
L
mF
2
k
15
RT
RT
k
VID
2
95
= 2% is the tolerance of
A
)
k
mV
EA
3 8
.
2
A
95
5
mV
m
EA
(5)
(6)
(7)