ADP222ACPZ-1218-R7 AD [Analog Devices], ADP222ACPZ-1218-R7 Datasheet - Page 5

• Manufacturer Part Number: ADP222ACPZ-1218-R7
• Description: Dual, 300 mA Output, Low Noise
• Manufacturer: AD [Analog Devices]

Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND
ADJ1, ADJ2, VOUT1, VOUT2 to GND
EN1, EN2 to GND
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination.
The
the junction temperature limits are exceeded. Monitoring
ambient temperature does not guarantee that T
specified temperature limits. In applications with high power
dissipation and poor thermal resistance, the maximum ambient
temperature may have to be derated. In applications with
moderate power dissipation and low PCB thermal resistance, the
maximum ambient temperature can exceed the maximum limit as
long as the junction temperature is within specification limits.
The junction temperature (T
ambient temperature (T
(P
package (θ
from the ambient temperature (T
using the formula
D
), and the junction-to-ambient thermal resistance of the
ADP222/ADP223/ADP224/ADP225
T
J
= T
JA
A
). Maximum junction temperature (T
+ (P
D
× θ
JA
)
A
), the power dissipation of the device
J
) of the device is dependent on the
A
) and power dissipation (P
can be damaged when
Rating
−0.3 V to +6 V
−0.3 V to VIN
−0.3 V to +6 V
−65°C to +150°C
−40°C to +125°C
JEDEC J-STD-020
J
is within the
J
) is calculated
D
Rev. B | Page 5 of 24
)
Junction-to-ambient thermal resistance (θ
based on modeling and calculation using a 4-layer board. θ
is highly dependent on the application and board layout. In
applications where high maximum power dissipation exists,
close attention to thermal board design is required. The value
of θ
environmental conditions. The specified value of θ
on a 4-layer, 4 in × 3 in, 2½ oz copper board, as per JEDEC
standards. For more information, see the
Note, A Design and Manufacturing Guide for the Lead Frame
Chip Scale Package (LFCSP).
Ψ
with units of °C/W. Ψ
calculation using a 4-layer board. The JESD51-12, Guidelines for
Reporting and Using Package Thermal Information, states that
thermal characterization parameters are not the same as thermal
resistances. Ψ
through multiple thermal paths rather than a single path as in
thermal resistance, θ
convection from the top of the package as well as radiation from
the package, factors that make Ψ
applications. Maximum junction temperature (T
from the board temperature (T
using the formula
Refer to JESD51-8 and JESD51-12 for more detailed
information about Ψ
THERMAL RESISTANCE
θ
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
8-Lead 2 mm × 2 mm LFCSP
ESD CAUTION
JA
JB
and Ψ
JA
is the junction-to-board thermal characterization parameter
T
may vary, depending on PCB material, layout, and
J
= T
JB
ADP222/ADP223/ADP224/ADP225
B
are specified for the worst-case conditions, that is, a
+ (P
JB
measures the component power flowing
D
× Ψ
JB
JB
JB
. Therefore, Ψ
JB
.
)
of the package is based on modeling and
B
) and power dissipation (P
JB
more useful in real-world
θ
50.2
JA
JB
thermal paths include
AN-772
JA
θ
31.7
) of the package is
JC
J
) is calculated
Application
Ψ
18.2
JA
JB
is based
D
Unit
°C/W
JA
)