EL7156_05 INTERSIL [Intersil Corporation], EL7156_05 Datasheet - Page 8

• Manufacturer Part Number: EL7156_05
• Description: High Performance Pin Driver
• Manufacturer: INTERSIL [Intersil Corporation]

Applications Information
Product Description
The EL7156 is a high performance 40MHz pin driver. It
contains two analog switches connecting V
Depending on the value of the IN pin, one of the two
switches will be closed and the other switch open. An output
enable (OE) is also supplied which opens both switches
simultaneously.
Due to the topology of the EL7156, both the V
can be connected to any voltage between the V
pins, but V
turning on the body diode at the output stage.
The EL7156 is available in both the 8 Ld SO and the 8 Ld
PDIP packages. The relevant package should be chosen
depending on the calculated power dissipation.
3-state Operation
When the OE pin is low, the output is 3-state (floating.) The
output voltage is the parasitic capacitance’s voltage. It can
be any voltage between V
previous state. At 3-state, the output voltage can be pushed
to any voltage between V
be pushed higher than V
diode at the output stage will turn on.
Supply Voltage Range and Input Compatibility
The EL7156 is designed for operation on supplies from 5V to
15V (4.5V to 16.5V maximum). The table on page 6 shows
the specifications for the relationship between the V
V
All input pins are compatible with both 3V and 5V CMOS
signals. With a positive supply (V
also compatible with TTL inputs.
Power Supply Bypassing
When using the EL7156, it is very important to use adequate
power supply bypassing. The high switching currents
developed by the EL7156 necessitate the use of a bypass
capacitor between the supplies (V
It is recommended that a 2.2µF tantalum capacitor be used
in parallel with a 0.1µF low-inductance ceramic MLC
capacitor. These should be placed as close to the supply
pins as possible. It is also recommended that the V
pins have some level of bypassing, especially if the EL7156
is driving highly capacitive loads.
Power Dissipation Calculation
When switching at high speeds, or driving heavy loads, the
EL7156 drive capability is limited by the rise in die
temperature brought about by internal power dissipation. For
reliable operation die temperature must be kept below
T
dissipation for a given application prior to selecting the
package type.
JMAX
H
, V
L
, and GND pins.
(125°C). It is necessary to calculate the power
H
must be greater than V
H
H
H
or lower than V
and V
and V
8
S
L
L
S
. The output voltage can’t
+) of 5V, the EL7156 is
, depending on the
+ & V
L
in order to prevent
S
L
-) and GND pins.
H
since the body
and V
H
S
and V
+ and V
L
H
S
to OUT.
and V
+, V
L
pins
S
S
-
-,
L
EL7156
Power dissipation may be calculated:
where:
Having obtained the application’s power dissipation, a
maximum package thermal coefficient may be determined,
to maintain the internal die temperature below T
where:
θ
PDIP8 package when using a standard JEDEC JESD51-3
single-layer test board. If T
calculated using the equation above, then one of the
following actions must be taken:
PD
θ
JA
JA
V
GND)
V
C
C
I
f is frequency
T
T
PD is the power dissipation calculated above
θ
Reduce θ
into the PCB (as compared to the standard JEDEC
JESD51-3)
Use the PDIP8 instead of the SO8 package
De-rate the application either by reducing the switching
frequency, the capacitive load, or the maximum operating
(ambient) temperature (T
S
JA
S
OUT
JMAX
MAX
VS
INT
is 160°C/W for the SO8 package and 100°C/W for the
=
is the quiescent supply current (3mA max)
=
is the total power supply to the EL7156 (from V
V
thermal resistance on junction to ambient
(
V
is the integral capacitance due to V
T
---------------------------------------- -
S
is the integral load capacitance due to V
is the swing on the output (V
JMAX
is the maximum operating temperature
S
+=V
is the maximum junction temperature (125°C)
10
15
×
5
JA
I
H
PD
S
TABLE 1. INTEGRAL CAPACITANCE
(V)
–
)
the system by designing more heat-sinking
+
T
(
MAX
C
VS
×
V
S
JMAX
2
MAX
×
C
f )
VS
)
+
80
85
90
is greater than 125°C when
(pF)
[
(
C
INT
H
- V
+
C
L
S
)
L
+
)
×
V
November 3, 2005
H
C
JMAX
OUT
INT
120
145
180
(pF)
S
2
:
FN7280.2
+ to
×
f
]