LT3755 LINER [Linear Technology], LT3755 Datasheet - Page 14

• Manufacturer Part Number: LT3755
• Description: 40VIN, 75VOUT LED Controller
• Manufacturer: LINER [Linear Technology]

at least 100ns to allow margin for PWM control latitude,
GATE rise/fall times and SW node rise/fall times.
Thermal Considerations
The LT3755 and LT3755-1 are rated to a maximum input
voltage of 40V. Careful attention must be paid to the internal
power dissipation of the IC at higher input voltages to en-
sure that a junction temperature of 125°C is not exceeded.
This junction limit is especially important when operating
at high ambient temperatures. The majority of the power
dissipation in the IC comes from the supply current needed
to drive the gate capacitance of the external power MOSFET.
This gate drive current can be calculated as:
A low Q
erating at high input voltages, and the switching frequency
should also be chosen carefully to ensure that the IC does
not exceed a safe junction temperature. The internal junc-
tion temperature of the IC can be estimated by:
where T
current of the part (maximum 1.7mA) and θ
package thermal impedance (68°C/W for the 3mm × 3mm
QFN package). For example, an application with T
= 85°C, V
with Q
will be approximately:
The Exposed Pad on the bottom of the package must be
soldered to a ground plane. This ground should then be
connected to an internal copper ground plane with thermal
vias placed directly under the package to spread out the
heat dissipated by the IC.
Frequency Synchronization (LT3755-1 Only)
The LT3755-1 switching frequency can be synchronized to
an external clock using the SYNC pin. For proper operation,
the R
LT3755/LT3755-1
APPLICATIONS INFORMATION
14
I
T
T
= 111°C
GATE
J
J
T
= T
= 85°C + [40V (1.7mA + 400kHz • 20nC) • 68°C/W]
resistor should be chosen for a switching frequency
G
G
A
= f
A
= 20nC, the maximum IC junction temperature
power MOSFET should always be used when op-
is the ambient temperature, I
IN(MAX)
+ [V
SW
• Q
IN
(I
= 40V, f
G
Q
+ f
SW
SW
• Q
= 400kHz, and having a FET
G
) • θ
JA
]
Q
is the quiescent
JA
A(MAX)
is the
20% lower than the external clock frequency. The SYNC
pin is disabled during the soft-start period.
Observation of the following guidelines about the SYNC
waveform will ensure proper operation of this feature.
Driving SYNC with a 50% duty cycle waveform is always
a good choice, otherwise, maintain the duty cycle between
20% and 60%. When using both PWM and SYNC features,
the PWM signal rising edge should occur at least 200ns
before the SYNC rising edge (V
performance. If the SYNC pin is not used, it should be
connected to GND.
Open LED Detection (LT3755)
The LT3755 provides an open-drain status pin, OPENLED,
that pulls low when the FB pin is within ~50mV of its
1.25V regulated voltage. If the open LED clamp voltage
is programmed correctly using the FB pin, then the FB
pin should never exceed 1.1V when LEDs are connected,
therefore, the only way for the FB pin to be within 50mV
of the 1.25V regulation voltage is for an open LED event to
have occurred when an open LED fault occurs, the output
may initially overshoot the FB regulation point by several
percent, due to slew rate limitations on VC and the absence
of any load on the output. In order to ensure the voltage
on switching components remains below programmed
limits, and to guarantee accurate reporting of the open
LED fault, adding a silicon diode between OPENLED and
SS is recommended, as well as a 10k resistor in series
with the soft-start capacitor, if one is used.
Input Capacitor Selection
The input capacitor supplies the transient input current for
the power inductor of the converter and must be placed
and sized according to the transient current requirements.
The switching frequency, output current and tolerable input
voltage ripple are key inputs to estimating the capacitor
value. An X7R type ceramic capacitor is usually the best
choice since it has the least variation with temperature and
DC bias. Typically, boost and SEPIC converters require a
lower value capacitor than a buck mode converter. As-
suming that a 100mV input voltage ripple is acceptable,
IH
) for optimal PWM
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