HIP6005 INTERSIL [Intersil Corporation], HIP6005 Datasheet - Page 8
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HIP6005
Manufacturer Part Number
HIP6005
Description
Buck Pulse-Width Modulator (PWM) Controller and Output Voltage Monitor
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
1.HIP6005.pdf
(12 pages)
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The compensation network consists of the error amplifier
(internal to the HIP6005) and the impedance networks Z
and Z
provide a closed loop transfer function with the highest 0dB
crossing frequency (f
Phase margin is the difference between the closed loop
phase at f
the compensation network’s poles, zeros and gain to the
components (R1, R2, R3, C1, C2, and C3) in Figure 8. Use
these guidelines for locating the poles and zeros of the
compensation network:
Compensation Break Frequency Equations
F
F
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
3. Place 2
4. Place 1
5. Place 2
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Z1
Z2
V
OSC
FIGURE 8. VOLTAGE-MODE BUCK CONVERTER COMPEN-
=
=
FB
OSC
----------------------------------
2
----------------------------------------------------- -
2
. The goal of the compensation network is to
0dB
COMPARATOR
R2 C1
ERROR
ST
ND
ST
ND
R1
1
V
PWM
E/A
SATION DESIGN
AMP
and 180 degrees The equations below relate
Zero Below Filter’s Double Pole (~75% F
Pole at the ESR Zero
Zero at Filter’s Double Pole
Pole at Half the Switching Frequency
+
1
-
+
Z
R3
FB
HIP6005
+
-
DETAILED COMPENSATION COMPONENTS
0dB
REFERENCE
C3
COMP
DRIVER
) and adequate phase margin.
C1
Z
IN
C2
DACOUT
+
F
F
-
8
P1
P2
R2
=
=
V
IN
------------------------------------------------------ -
2
----------------------------------
2
PHASE
(PARASITIC)
Z
R2
R3 C3
FB
L
1
O
FB
C3
1
Z
--------------------- -
C1
C1 C2
ESR
IN
R1
C
O
R3
+
C2
V
OUT
LC
V
)
OUT
IN
HIP6005
Figure 9 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 9. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at F
the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 9 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
Z
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and voltage rating
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
FIGURE 9. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
FB
100
-20
-40
-60
80
60
40
20
0
and Z
10
(R
20LOG
2
IN
MODULATOR
/R
1
to provide a stable, high bandwidth (BW) overall
)
100
GAIN
1K
F
Z1
F
FREQUENCY (Hz)
LC
F
Z2
10K
F
P1
F
(V
ESR
P2
100K
IN
20LOG
F
/ V
with the capabilities of
P2
OSC
OPEN LOOP
ERROR AMP GAIN
1M
)
COMPENSATION
GAIN
CLOSED LOOP
GAIN
10M