ML4830CP MICRO-LINEAR [Micro Linear Corporation], ML4830CP Datasheet - Page 6

• Manufacturer Part Number: ML4830CP
• Description: Electronic Ballast Controller
• Manufacturer: MICRO-LINEAR [Micro Linear Corporation]

ML4830
The output of the gain modulator appears as a voltage
across the 14K resistor (Figure 1) on the positive terminal
of IA to form the reference for the current error amplifier.
When the loop is in regulation, the negative voltage on
IA+/I(LIM) (Pin 4) keeps the positive terminal of IA at 0V.
The output of the gain modulator is limited to 0.88V.
AVERAGE CURRENT AND OUTPUT VOLTAGE
REGULATION
The PWM regulator in the PFC Control section will act to
offset the positive voltage caused by the multiplier output
by producing an offsetting negative voltage on the current
sense resistor at Pin 4. A cycle-by-cycle current limit is
included to protect the MOSFET from high speed current
transients. When the voltage at Pin 4 goes negative by
more than 1V, the PFC cycle is terminated.
For more information on compensating the average
current and boost voltage error amplifier loops, see
Application Note 16 .
6
12
10
17
18
13
11
20
19
2
1
4
3
where: I(SINE) is the current in the dropping resistor,
–1V
R(X)/C(X)
INTERRUPT
VCC
V
GND
OVP/INHIBIT
IA OUT
IA –
IA+/
I(LIM)
I(SINE)
EA OUT
EA –
REF
V
V
REF
MUL
V(EA) is the output of the error amplifier (Pin 20).
UNDER-VOLTAGE
+
–
I(LIM)
AND THERMAL
SHUTDOWN
14K
MODULATORS
+
–
0 034
V
.
GAIN
REF
5V
I SINE
+
–
–
+
–
+
(
EA
IA
) (
2.6V
VEA
INH
–
+
LFB OUT
A1
INTERRUPT
1 1
PREHEAT
+
–
TIMER
. ) (
AND
Figure 1. ML4830 Block Diagram
14
+
–
k
)
6.8V
(1)
S
+
–
R
Q
VCO–O
OVERVOLTAGE PROTECTION AND INHIBIT
The OVP/INHIBIT pin serves to protect the power circuit
from being subjected to excessive voltages if the load
should change suddenly (lamp removal). A divider from
the high voltage DC bus (Figure 8: R14, R24) sets the
OVP trip level. When the voltage on Pin 11 exceeds 5V,
the PFC transistor is inhibited. The ballast section will
continue to operate. If Pin 11 is driven above 6.8V, the
IC is inhibited and goes into the low quiescent mode.
The OVP threshold should be set to a level where the
power components are safe to operate, but not so low
as to interfere with the boost voltage regulation loop
(R11, R12, R23).
BALLAST OUTPUT SECTION
The IC controls output power to the lamps in one of three
different modes. The Mode pin (Pin 8) sets the operating
mode of the IC. With Pin 8 at GND, the output section is
in the Frequency Modulation mode with non-overlapping
conduction, which means that both ballast output drivers
will be low during t
(VCO-O), Pin 8 is left open and the transition from OUT A
high to OUT B high occurs with no dead time. This mode
is typically used in current fed ballast topologies.
PWM
S
Q
R
T
Q
Q
OSCILLATOR
VCO–O PWM
LOGIC
DIS
(Figure 2). In the overlapping mode
CLK
2.5V
–
+
I
R(SET)
LAMP F.B.
PFC OUT
R(T)/C(T)
LFB OUT
MODE
OUT A
OUT B
R(SET)
16
15
14
8
6
5
7
9