EMC12 ETC2 [List of Unclassifed Manufacturers], EMC12 Datasheet - Page 30

• Manufacturer Part Number: EMC12
• Description: Audio Interface for the EmPack System
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

EMC12 Hardware Reference Manual
1.4
EMC12 DSP
The EMC12 is optionally populated with one Agere DSP32C, an 80 MHz, 20 MIPs, 40 MFlops digital
signal processor chip. It is packaged in a 164-pin bumpered quad flat pack (BQFP). The DSP32C may
be operated from 50MHz to 80 MHz.
The DSP is controlled by an FPGA (Xilinx 4013E) which provides address decoding for the parallel ports,
external interrupt control, TDM interface, and interface to the status LEDs.
1.4.1 DSP Reset
The RESTN pin of the DSP is controlled by the DSP_RESET bit in BCR0. Writing a ‘0’ to this bit halts
the DSP. This bit is ‘0’ after power-up and board reset.
A transition from ‘0’ to ‘1’ of this bit initiates the DSP reset sequence. Refer to the DSP32C
Information Manual for in-depth discussion of halt and reset operations of the DSP.
1.4.2 DSP Interrupts
The two external interrupt pins of the DSP32C, INTREQ1 and INTREQ2, are controlled by the DSP
Interrupt Control Register (DICR) in the FPGA. The various external interrupt operations and their
control values are shown in Table 10.
1.4.3 DSP Clock
The serially programmable frequency generator ICS AV9110-02CS14 operates from a reference clock
of 14.318 MHz (REFCLK) available on the mezzanine connector. The output clock (CLK/X) from the
AV9110 is then distributed to the local clock multipliers ICS AV9170-01CS8 which quadruple the
frequency. The programmability of the AV9110 lets the DSP clock frequency be selected in software.
The local clock multipliers allow the AV9110 output clock to be distributed over a long distance at
relatively low frequencies. TDI is connected to the DATA pin of the AV9110, and TCK is inverted and
connected to the SCLK pin. To program the AV9110, set the AV9110_EN bit of BCR1 to select the
AV9110, shift the serial data using TDI and TCK, and reset the AV9110_EN bit in BCR1 to deselect the
AV9110.
Table 1-19 shows the format of the serial data shifted into the AV9110.
Note that bit 0 is the first bit shifted into the device.
09 Jan 2006
Communication Automation Corporation
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