RF6001_1 RFMD [RF Micro Devices], RF6001_1 Datasheet - Page 36

• Manufacturer Part Number: RF6001_1
• Description: FRACTIONAL-N RF SYNTHESIZER WITH MODULATOR AND DIGITAL IF FILTER
• Manufacturer: RFMD [RF Micro Devices]

RF6001
Part of the POLARIS™ TOTAL RADIO™ Solution
Case 5: GMSK FIFO Clocking Signals Generated by Baseband, TXD_MODE=1, TXF=11
In this FIFO mode, the baseband will generate a pulse equal to one clock period on the MS line to signify the beginning of a
FIFO data transfer. If the SDI bit MS_LOC is programmed low then the transfer of the first data bit will occur on the same clock
period as the pulse on MS. With MS_LOC low there does not have to be any idle clock pulses between transfer intervals. If
MS_LOC is high then the transfer of the first data bit will occur on the next clock period after the pulse on MS. With MS_LOC
high there must be at least one idle clock pulse between the end of the last transfer interval and the beginning of the next.
The baseband will then generate a clock of less than or equal to 26MHz applied to MCK. On every rising edge of MCK, the
baseband will assert an NRZ data bit on MDI if TXCKINV is low. The RF6001 will read this data on every falling edge of MCK if
TXCKINV is set low. If TXCKINV is set high then the baseband will assert an NRZ data bit on MDI on every falling edge of MCK
and the RF6001 will read the data bit on every rising edge of MCK. This data will be stored in a FIFO register of length 1024
bits in the RF6001.
Data will continue to be read in until the number of bits read becomes equal to the setting of the SDI word MS_LEN. MS_LEN
can be set to 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16, 24, 32, or 48 bits. Once this occurs, no further data will be read until
another pulse is applied to MS to start the process over.
The diagram below summarizes this mode of the interface.
Transmission is initiated by setting the TXST or TXEN pins to a logical high. If TX_ST is set high then an internal timer, TXENU, is
programmed to delay the rise of TX_EN. A second timer, MD_DLY, determines when the modulation stored in the FIFO will begin
to be output relative to the rising edge of TX_ST. Data will be output at a 13MHz/48 rate. New data CAN be loaded into the
FIFO input while the output is active. The diagram below summarizes the operation of the second step of this interface.
Note that there are NOT TXD_MODE=0 cases for the FIFO system (i.e., the baseband is always the master of FIFO data trans-
fers.)
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Count
Count
Count
Count
MCK
FIFO
FIFO
MCK
FIFO
FIFO
MDI
MDI
MS
MS
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MS_LOC=0
MS_LOC=1
MS_LOC=0
MS_LOC=1
1
1
TXCKINV=0, MS_LEN=4, TXF=11
TXCKINV=1, MS_LEN=4, TXF=11
2
1
2
1
3
2
3
2
4
3
4
3
4
4
5
5
6
6
5
5
Rev A3 DS050929