AT32UC3A0512-ALTES ATMEL [ATMEL Corporation], AT32UC3A0512-ALTES Datasheet
AT32UC3A0512-ALTES
Related parts for AT32UC3A0512-ALTES
AT32UC3A0512-ALTES Summary of contents
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... One Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible • One 8-channel 10-bit Analog-To-Digital Converter • 16-bit Stereo Audio Bitstream – Sample Rate KHz ® 32-Bit Microcontroller ® AVR 32 32-Bit Microcontroller AT32UC3A0512 AT32UC3A0256 AT32UC3A0128 AT32UC3A1512 AT32UC3A1256 AT32UC3A1128 Preliminary Summary 32058FS–AVR32–08/08 ...
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On-Chip Debug System (JTAG interface) – Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace • 100-pin TQFP (69 GPIO pins), 144-pin LQFP (109 GPIO pins) • 5V Input Tolerant I/Os • Single 3.3V Power Supply or Dual ...
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Description The AT32UC3A is a complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies MHz. AVR32 high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular empha- ...
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... Configuration Summary The table below lists all AT32UC3A memory and package configurations: Device AT32UC3A0512 AT32UC3A0256 AT32UC3A0128 AT32UC3A1512 AT32UC3A1256 AT32UC3A1128 3. Abbreviations • GCLK: Power Manager Generic Clock • GPIO: General Purpose Input/Output • HSB: High Speed Bus • MPU: Memory Protection Unit • ...
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Blockdiagram Figure 4-1. Blockdiagram TC K JTAG TD O INTERFACE [5..0] M SEO [1..0] EVTI_N EVTO _N VBU USB D - INTERFACE ID VBOF DM A ...
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Processor and architecture 4.1.1 AVR32 UC CPU • 32-bit load/store AVR32A RISC architecture. – 15 general-purpose 32-bit registers. – 32-bit Stack Pointer, Program Counter and Link Register reside in register file. – Fully orthogonal instruction set. – Privileged and ...
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Peripheral Bus A able to run on at divided bus speeds compared to the High Speed Bus Figure 4-1 same clock, but the clock to each module can be individually shut off by the Power Manager. The figure identifies ...
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Signals Description The following table gives details on the signal name classified by peripheral The signals are multiplexed with GPIO pins as described in on page Table 5-1. Signal Description List Signal Name Function VDDPLL Power supply for PLL ...
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Table 5-1. Signal Description List Signal Name Function MSEO0 - MSEO1 Trace Frame Control EVTI_N Event In EVTO_N Event Out GCLK0 - GCLK3 Generic Clock Pins RESET_N Reset Pin RTC_CLOCK RTC clock WDTEXT External Watchdog Pin EXTINT0 - EXTINT7 External ...
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Table 5-1. Signal Description List Signal Name Function ADDR0 - ADDR23 Address Bus CAS Column Signal DATA0 - DATA15 Data Bus NCS0 - NCS3 Chip Select NRD Read Signal NWAIT External Wait Signal NWE0 Write Enable 0 NWE1 Write Enable ...
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Table 5-1. Signal Description List Signal Name Function RX_DATA SSC Receive Data RX_FRAME_SYNC SSC Receive Frame Sync TX_CLOCK SSC Transmit Clock TX_DATA SSC Transmit Data TX_FRAME_SYNC SSC Transmit Frame Sync A0 Channel 0 Line A A1 Channel 1 Line A ...
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Table 5-1. Signal Description List Signal Name Function AD0 - AD7 Analog input pins ADVREF Analog positive reference voltage input PWM0 - PWM6 PWM Output Pins DDM USB Device Port Data - DDP USB Device Port Data + VBUS USB ...
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Package and Pinout The device pins are multiplexed with peripheral functions as described in Figure 6-1. TQFP100 Pinout Table 6-1. TQFP100 Package Pinout 1 PB20 2 PB21 3 PB22 4 VDDIO 5 GND 6 PB23 7 PB24 8 PB25 ...
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Table 6-1. TQFP100 Package Pinout 23 PA02 24 PA03 25 PA04 Figure 6-2. LQFP144 Pinout Table 6-2. VQFP144 Package Pinout 1 PX00 2 PX01 3 PB20 4 PX02 5 PB21 6 PB22 7 VDDIO 8 GND 9 PB23 10 PX03 ...
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Table 6-2. VQFP144 Package Pinout 22 PB31 23 RESET_N 24 PX05 25 PA00 26 PX06 27 PA01 28 GND 29 VDDCORE 30 PA02 31 PX07 32 PA03 33 PX08 34 PA04 35 PX09 36 VDDIO 32058FS–AVR32–08/08 58 PA16 94 59 ...
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Power Considerations 7.1 Power Supplies The AT32UC3A has several types of power supply pins: • VDDIO: Powers I/O lines. Voltage is 3.3V nominal. • VDDANA: Powers the ADC Voltage is 3.3V nominal. • VDDIN: Input voltage for the voltage ...
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Voltage Regulator 7.2.1 Single Power Supply The AT32UC3A embeds a voltage regulator that converts from 3.3V to 1.8V. The regulator takes its input voltage from VDDIN, and supplies the output voltage on VDDOUT. VDDOUT should be externally connected to ...
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Analog-to-Digital Converter (A.D.C) reference. The ADC reference (ADVREF) must be provided from an external source. Two decoupling capacitors must be used to insure proper decoupling. Refer to In case ADC is not used, the ADVREF pin should be connected ...
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I/O Line Considerations 8.1 JTAG pins TMS, TDI and TCK have pull-up resistors. TDO is an output, driven VDDIO, and has no pull-up resistor. 8.2 RESET_N pin The RESET_N pin is a schmitt input and integrates ...
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... KBytes (AT32UC3A0256, AT32UC3A1256) – 128 KBytes (AT32UC3A1128, AT32UC3A2128) • Internal High-Speed SRAM, Single-cycle access at full speed – 64 KBytes (AT32UC3A0512, AT32UC3A0256, AT32UC3A1512, AT32UC3A1256) – 32KBytes (AT32UC3A1128) 9.2 Physical Memory Map The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot ...
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... Table 9-2. Flash Memory Parameters Flash Size Part Number (FLASH_PW) AT32UC3A0512 512 Kbytes AT32UC3A1512 512 Kbytes AT32UC3A0256 256 Kbytes AT32UC3A1256 256 Kbytes AT32UC3A1128 128 Kbytes AT32UC3A0128 128 Kbytes 9.3 Bus Matrix Connections Accesses to unused areas returns an error result to the master requesting such an access. ...
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Figure 9-1. 32058FS–AVR32–08/08 HMatrix Master / Slave Connections 0 1 CPU Data 0 CPU 1 Instruction CPU SAB 2 PDCA 3 MACB 4 USBB DMA 5 AT32UC3A HMATRIX SLAVES ...
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Peripherals 10.1 Peripheral address map Table 10-1. Peripheral Address Mapping Address 0xE0000000 0xFFFE0000 0xFFFE1000 0xFFFE1400 0xFFFE1800 0xFFFE1C00 0xFFFE2000 0xFFFF0000 0xFFFF0800 0xFFFF0C00 0xFFFF0D00 0xFFFF0D30 0xFFFF0D80 0xFFFF1000 0xFFFF1400 0xFFFF1800 32058FS–AVR32–08/08 Peripheral Name USBB USBB Slave Interface - USBB USBB USBB Configuration ...
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Table 10-1. Peripheral Address Mapping (Continued) Address 0xFFFF1C00 0xFFFF2000 0xFFFF2400 0xFFFF2800 0xFFFF2C00 0xFFFF3000 0xFFFF3400 0xFFFF3800 0xFFFF3C00 10.2 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being ...
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The following GPIO registers are mapped on the local bus: Table 10-2. Port 32058FS–AVR32–08/08 Local bus mapped GPIO registers Register Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) Output Driver Enable Register ...
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Table 10-2. Port 3 10.3 Interrupt Request Signal Map The various modules may output Interrupt request signals. These signals are routed to the Inter- rupt Controller (INTC), described in a later chapter. The Interrupt Controller supports groups ...
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Table 10-3. 32058FS–AVR32–08/08 Interrupt Request Signal Map 0 General Purpose Input/Output 1 General Purpose Input/Output 2 General Purpose Input/Output 3 General Purpose Input/Output 4 General Purpose Input/Output 5 General Purpose Input/Output 6 General Purpose Input/Output 2 7 General Purpose Input/Output ...
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Table 10-3. 10.4 Clock Connections 10.4.1 Timer/Counters Each Timer/Counter channel can independently select an internal or external clock source for its counter: Table 10-4. Source Internal External 10.4.2 USARTs Each USART can be connected to an internally divided clock: Table ...
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SPIs Each SPI can be connected to an internally divided clock: Table 10-6. SPI 0 1 10.5 Nexus OCD AUX port connections If the OCD trace system is enabled, the trace system will take control over a number of ...
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Table 10-8. PID Value 10.7 Peripheral Multiplexing on I/O lines Each GPIO line can be assigned to one of 3 peripheral functions ...
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Table 10-9. GPIO Controller Function Multiplexing 41 58 PA16 42 60 PA17 43 62 PA18 44 64 PA19 45 66 PA20 51 73 PA21 52 74 PA22 53 75 PA23 54 76 PA24 55 77 PA25 56 78 PA26 57 ...
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Table 10-9. GPIO Controller Function Multiplexing 7 11 PB24 8 13 PB25 9 14 PB26 10 15 PB27 14 19 PB28 15 20 PB29 16 21 PB30 17 22 PB31 63 85 PC00 64 86 PC01 85 124 PC02 86 ...
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Table 10-9. GPIO Controller Function Multiplexing 99 PX25 101 PX26 103 PX27 105 PX28 107 PX29 110 PX30 112 PX31 114 PX32 118 PX33 120 PX34 135 PX35 137 PX36 140 PX37 142 PX38 144 PX39 10.8 Oscillator Pinout The ...
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GPIO The GPIO open drain feature (GPIO ODMER register (Open Drain Mode Enable Register)) is not available for this device. 10.11 Peripheral overview 10.11.1 External Bus Interface • Optimized for Application Memory Space support • Integrates Two External Memory ...
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Supports Mobile SDRAM Devices • Error Detection – Refresh Error Interrupt • SDRAM Power-up Initialization by Software • CAS Latency Supported • Auto Precharge Command Not Used 10.11.4 USB Controller • USB 2.0 Compliant, Full-/Low-Speed ...
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Optional Manchester Encoding • RS485 with driver control signal • ISO7816 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • IrDA modulation and demodulation ...
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Ethernet 10/100 MAC • Compatibility with IEEE Standard 802.3 • 10 and 100 Mbits per second data throughput capability • Full- and half-duplex operations • MII or RMII interface to the physical layer • Register Interface to address, data, ...
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Boot Sequence This chapter summarizes the boot sequence of the AT32UC3A. The behaviour after power-up is controlled by the Power Manager. For specific details, refer to (PM)” on page 11.1 Starting of clocks After power-up, the device will be ...
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Electrical Characteristics 12.1 Absolute Maximum Ratings* Operating Temperature......................................-40⋅C to +85⋅C Storage Temperature .......................................................... ....- 60°C to +150°C Voltage on Input Pin with respect to Ground-O.3V to 5.5V Maximum Operating Voltage (VDDCORE, VDDPLL) ..... 1.95V Maximum Operating Voltage (VDDIO).............................. 3.6V ...
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DC Characteristics The following characteristics are applicable to the operating temperature range: T ified and are certified for a junction temperature Symbol Parameter V VDDCOR DC Supply Core Supply PLL VDDPLL V DC ...
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Regulator characteristics 12.3.1 Electrical characteristics Symbol Parameter V Supply voltage (input) VDDIN V Supply voltage (output) VDDOUT Maximum DC output current with V I OUT Maximum DC output current with V 12.3.2 Decoupling requirements Symbol Parameter C Input Regulator ...
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Power Consumption The values in tion with operating conditions as follows: •V DDIO •V DDCORE •T = 25° •I/Os are inactive Figure 12-1. Measurement setup 32058FS–AVR32–08/08 Table 12-2 and Table 12-3 on page 43 = 3.3V = ...
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These figures represent the power consumption measured on the power supplies. Table 12-2. Power Consumption for Different Modes Mode Conditions CPU running from flash. CPU clocked from PLL0 at f MHz Voltage regulator is on. XIN0 : external clock. XIN1 ...
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Clock Characteristics These parameters are given in the following conditions: • V DDCORE • Ambient Temperature = 25°C 12.6.1 CPU/HSB Clock Characteristics Table 12-4. Core Clock Waveform Parameters Symbol Parameter 1/(t ) CPU Clock Frequency CPCPU t CPU Clock ...
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KHz Oscillator Characteristics Table 12-8. 32 KHz Oscillator Characteristics Symbol Parameter 1/(t ) Crystal Oscillator Frequency CP32KHz Duty Cycle C Equivalent Load Capacitance L t Startup Time ST I Current Consumption OSC Note the equivalent ...
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ADC Characteristics Table 12-11. Channel Conversion Time and ADC Clock Parameter ADC Clock Frequency ADC Clock Frequency Startup Time Track and Hold Acquisition Time Conversion Time Conversion Time Throughput Rate Throughput Rate Notes: 1. Corresponds to 13 clock cycles ...
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EBI Timings These timings are given for worst case process 85⋅C, VDDCORE = 1.65V, VDDIO = 3V and 40 pF load capacitance. Table 12-15. SMC Clock Signal. Symbol Parameter 1/(t ) SMC Controller Clock Frequency CPSMC Note: ...
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Table 12-17. SMC Read Signals with no Hold Settings Symbol Parameter SMC Data Setup before NRD High 19 Data Hold after NRD High SMC 20 SMC Data Setup before NCS High 21 SMC Data Hold after NCS High 22 Table ...
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Table 12-19. SMC Write Signals with No Hold Settings (NWE Controlled only). Symbol Parameter NWE Rising to A2-A25 Valid SMC 37 NWE Rising to NBS0/A0 Valid SMC 38 NWE Rising to NBS1 Change SMC 39 NWE Rising to A1/NBS2 Change ...
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Figure 12-3. SMC Signals for NRD and NRW Controlled Accesses. A2-A25 A0/A1/NBS[3:0] NCS SMC9 NRD SMC19 D0 - D15 NWE 12.9.1 SDRAM Signals These timings are given for 10 pF load on SDCK and other signals. Table ...
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Table 12-21. SDRAM Clock Signal. Symbol SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC SDRAMC 32058FS–AVR32–08/08 Parameter Address Change before SDCK Rising Edge 11 Address Change after SDCK Rising Edge 12 Bank Change before SDCK ...
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Figure 12-4. SDRAMC Signals relative to SDCK. SDCK SDRAMC SDRAMC SDRAMC 1 2 SDCKE SDCS RAS CAS SDWE SDA10 A0 - A9, A11 - A13 BA0/BA1 DQM0 - DQM3 D0 - D15 Read D0 - D15 to Write 32058FS–AVR32–08/08 SDRAMC ...
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JTAG Timings 12.10.1 JTAG Interface Signals Table 12-22. JTAG Interface Timing specification Symbol Parameter JTAG TCK Low Half-period 0 JTAG TCK High Half-period 1 JTAG TCK Period 2 JTAG TDI, TMS Setup before TCK High 3 JTAG TDI, TMS ...
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Figure 12-5. JTAG Interface Signals TCK TMS/TDI TDO Device Inputs Device Outputs 12.11 SPI Characteristics Figure 12-6. SPI Master mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1) SPCK MISO MOSI 32058FS–AVR32–08/08 JTAG 2 JTAG 0 JTAG JTAG ...
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Figure 12-7. SPI Master mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0) SPCK MISO MOSI Figure 12-8. SPI Slave mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0) SPCK MISO MOSI Figure 12-9. SPI Slave mode with (CPOL = ...
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Table 12-23. SPI Timings Symbol Parameter SPI MISO Setup time before SPCK rises (master) 0 SPI MISO Hold time after SPCK rises (master) 1 SPI SPCK rising to MOSI Delay (master) 2 SPI MISO Setup time before SPCK falls (master) ...
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Table 12-25. Ethernet MAC MII Specific Signals Symbol Parameter EMAC Hold for ERX from ERXCK 12 EMAC Setup for ERXER from ERXCK 13 EMAC Hold for ERXER from ERXCK 14 EMAC Setup for ERXDV from ERXCK 15 EMAC Hold for ...
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Table 12-26. Ethernet MAC RMII Specific Signals Symbol EMAC EMAC EMAC EMAC EMAC EMAC EMAC EMAC Figure 12-11. Ethernet MAC RMII Mode EREFCK ETXEN ETX[1:0] ERX[1:0] ERXER ECRSDV 12.13 Flash Characteristics The following table gives the device maximum operating frequency ...
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Mechanical Characteristics 13.1 Thermal Considerations 13.1.1 Thermal Data Table 13-1 Table 13-1. Symbol θ JA θ JC θ JA θ JC 13.1.2 Junction Temperature The average chip-junction temperature where: • θ = package thermal ...
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Package Drawings Figure 13-1. TQFP-100 package drawing Table 13-2. Device and Package Maximum Weight TBD Table 13-3. Package Characteristics Moisture Sensitivity Level Table 13-4. Package Reference JEDEC Drawing Reference JESD97 Classification 32058FS–AVR32–08/08 mg TBD MS-026 E3 AT32UC3A 60 ...
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Figure 13-2. LQFP-144 package drawing Table 13-5. Device and Package Maximum Weight TBD Table 13-6. Package Characteristics Moisture Sensitivity Level Table 13-7. Package Reference JEDEC Drawing Reference JESD97 Classification 32058FS–AVR32–08/08 mg TBD MS-026 E3 AT32UC3A 61 ...
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Soldering Profile Table 13-8 Table 13-8. Profile Feature Average Ramp-up Rate (217°C to Peak) Preheat Temperature 175°C ±25°C Temperature Maintained Above 217°C Time within 5⋅C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25⋅C to Peak Temperature ...
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... Ordering Information Table 14-1. Ordering Information Device Ordering Code AT32UC3A0512 AT32UC3A0512-ALUT AT32UC3A0512-ALUR AT32UC3A0512-ALTR AT32UC3A0512-ALTT AT32UC3A0512-ALTES AT32UC3A0256 AT32UC3A0256-ALUT AT32UC3A0256-ALUR AT32UC3A0128 AT32UC3A0128-ALUT AT32UC3A0128-ALUR AT32UC3A1512 AT32UC3A1512-AUT AT32UC3A1512-AUR AT32UC3A1256 AT32UC3A1256-AUT AT32UC3A1256-AUR AT32UC3A1128 AT32UC3A1128-AUT AT32UC3A1128-AUR 14.1 Automotive Quality Grade The AT32UC3A have been developed and manufactured according to the most stringent requirements of the international standard ISO-TS-16949 ...
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Errata All industrial parts labelled with -UES (engineering samples) are revision E parts. 15.1 Rev. J 15.1.1 PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), ...
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SPI Bad Serial Clock Generation on 2nd chip_select when SCBR = 1, CPOL=1 and NCPHA=0 When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't equal to 1, and ...
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Processor and Architecture 1. LDM instruction with PC in the register list and without ++ increments Rp For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie the pointer ...
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Rev. I 15.2.1 PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and ...
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... VDDCORE max and disable the BOD. 15.2.5 Flashc 1. On AT32UC3A0512 and AT32UC3A1512, corrupted read in flash after FLASHC WP, EP, EA, WUP, EUP commands may happen - After a FLASHC Write Page (WP) or Erase Page (EP) command applied to a page in a given half of the flash (first or last 256 kB of flash), reading (data read or code fetch) the other half of the flash may fail ...
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Workaround/fix The same PID should not be assigned to more than one channel. 15.2.7 GPIO 1. Some GPIO VIH (input high voltage) are 3.6V max instead of 5V tolerant Only 11 GPIOs remain 5V tolerant (VIHmax=5V): PB01, PB02, PB03, PB10, ...
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Rev. H 15.3.1 PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and ...
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... VDDCORE max and disable the BOD. 15.3.5 FLASHC 1. On AT32UC3A0512 and AT32UC3A1512, corrupted read in flash after FLASHC WP, EP, EA, WUP, EUP commands may happen - After a FLASHC Write Page (WP) or Erase Page (EP) command applied to a page in a given half of the flash (first or last 256 kB of flash), reading (data read or code fetch) the other half of the flash may fail ...
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This may lead to an exception or to other errors derived from this corrupted read access. Fix/Workaround Flashc WP, EP, EA, WUP, EUP commands: ...
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Rev. E 15.4.1 SPI 1. SPI FDIV option does not work Selecting clock signal using FDIV = 1 does not work as specified. Fix/Workaround Do not set FDIV = 1. 2. SPI Slave / PDCA transfer UNDERRUN ...
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Fix/workaround When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if CPOL=1 and CPHA=0. 15.4.2 PWM 1. PWM counter restarts at 0x0001 The PWM counter restarts at 0x0001 and not ...
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USB 1. USB No end of host reset signaled upon disconnection In host mode, in case of an unexpected device disconnection whereas a usb reset is being sent by the usb controller, the UHCON.RESET bit may not been cleared ...
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CPU Cycle Counter does not reset the COUNT system register on COMPARE match. The device revision E does not reset the COUNT system register on COMPARE match. In this revision, the COUNT register is clocked by the CPU clock, ...
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CPU cannot operate on a divided slow clock (internal RC oscillator) Fix/Workaround Do not run the CPU on a divided slow clock. 15.4.6 SDRAMC 1. Code execution from external SDRAM does not work Code execution from SDRAM does not ...
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Add an external inverter to the DCD line. 15.4.8 Power Manager 1. Voltage regulator input and output is connected to VDDIO and VDDCORE inside the device The voltage regulator input and output is connected to VDDIO and VDDCORE respectively inside ...
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... The command Quick Page Read User Page(QPRUP) is not functional. Fix/Workaround None. 3. PAGEN Semantic Field for Program GP Fuse Byte is WriteData[7:0], ByteAddress[1:0] on revision E instead of WriteData[7:0], ByteAddress[2:0]. Fix/Workaround None AT32UC3A0512 and AT32UC3A1512, corrupted read in flash after FLASHC WP, EP, EA, WUP, EUP commands may happen 32058FS–AVR32–08/08 AT32UC3A 79 ...
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After a FLASHC Write Page (WP) or Erase Page (EP) command applied to a page in a given half of the flash (first or last 256 kB of flash), reading (data read or code fetch) the other half of ...
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For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the increment of the pointer ...
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Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 16.1 Rev. F – 08/ 16.2 Rev. ...
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Rev. A – 03/07 1. 32058FS–AVR32–08/08 Updated ”USB On-The-Go Interface (USBB)” on page Updated ”JTAG and Boundary Scan” on page 750 Add description for silicon Rev G. Initial revision. AT32UC3A 517. with programming procedure . 83 ...
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Table of Contents 1 Description ............................................................................................... 3 2 Configuration Summary .......................................................................... 4 3 Abbreviations ........................................................................................... 4 4 Blockdiagram ........................................................................................... 5 5 Signals Description ................................................................................. 8 6 Package and Pinout ............................................................................... 13 7 Power Considerations ........................................................................... 16 8 I/O Line Considerations ...
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Boot Sequence ....................................................................................... 38 11.1Starting of clocks ...................................................................................................38 11.2Fetching of initial instructions ................................................................................38 12 Electrical Characteristics ...................................................................... 39 12.1Absolute Maximum Ratings* .................................................................................39 12.2DC Characteristics ................................................................................................40 12.3Regulator characteristics .......................................................................................41 12.4Analog characteristics ...........................................................................................41 12.5Power Consumption ..............................................................................................42 12.6Clock Characteristics ...
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Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to ...