DSPIC30F6012 MICROCHIP [Microchip Technology], DSPIC30F6012 Datasheet - Page 224

• Manufacturer Part Number: DSPIC30F6012
• Description: High-Performance, 16-Bit Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

dsPIC30F6011A/6012A/6013A/6014A
Timing Requirements
Timing Specifications
Trap Vectors........................................................................ 48
Traps ................................................................................... 47
DS70143C-page 222
Band Gap Start-up Time ........................................... 188
Brown-out Reset ....................................................... 187
CAN Module I/O ........................................................ 205
CLKO and I/O ........................................................... 186
DCI Module
External Clock ........................................................... 183
I
I
Input Capture ............................................................ 191
Oscillator Start-up Timer ........................................... 187
Output Compare Module........................................... 191
Power-up Timer ........................................................ 187
Reset......................................................................... 187
Simple OC/PWM Mode ............................................. 192
SPI Module
Type A Timer External Clock .................................... 189
Type B Timer External Clock .................................... 190
Type C Timer External Clock .................................... 190
Watchdog Timer........................................................ 187
PLL Clock.................................................................. 184
Hard and Soft .............................................................. 48
Sources ....................................................................... 47
2
2
C Bus Data (Master Mode)..................................... 202
C Bus Data (Slave Mode)....................................... 203
AC-Link Mode ................................................... 195
Multichannel, I
Master Mode (CKE = 0) .................................... 196
Master Mode (CKE = 1) .................................... 198
Slave Mode (CKE = 0) ...................................... 199
Slave Mode (CKE = 1) ...................................... 200
Address Error Trap ............................................. 47
Math Error Trap................................................... 47
Oscillator Fail Trap.............................................. 48
Stack Error Trap.................................................. 48
2
S Modes ................................... 194
U
UART Module
UART Operation
Unit ID Locations .............................................................. 145
Universal Asynchronous Receiver Transmitter. See UART.
W
Wake-up from Sleep ......................................................... 145
Wake-up from Sleep and Idle ............................................. 49
Watchdog Timer
Watchdog Timer (WDT)............................................ 145, 156
WWW Address ................................................................. 223
WWW, On-Line Support ....................................................... 8
Address Detect Mode ............................................... 107
Auto Baud Support ................................................... 108
Baud Rate Generator ............................................... 107
Enabling and Setting Up ........................................... 105
Framing Error (FERR) .............................................. 107
Idle Status................................................................. 107
Loopback Mode ........................................................ 107
Operation During CPU Sleep and Idle Modes .......... 108
Overview................................................................... 103
Parity Error (PERR) .................................................. 107
Receive Break .......................................................... 107
Receive Buffer (UxRXB) ........................................... 106
Receive Buffer Overrun Error (OERR Bit) ................ 106
Receive Interrupt ...................................................... 106
Receiving Data ......................................................... 106
Receiving in 8-bit or 9-bit Data Mode ....................... 106
Reception Error Handling ......................................... 106
Transmit Break ......................................................... 106
Transmit Buffer (UxTXB) .......................................... 105
Transmit Interrupt ..................................................... 106
Transmitting Data ..................................................... 105
Transmitting in 8-bit Data Mode................................ 105
Transmitting in 9-bit Data Mode................................ 105
UART1 Register Map................................................ 109
UART2 Register Map................................................ 109
Idle Mode .................................................................. 108
Sleep Mode .............................................................. 108
Timing Characteristics .............................................. 187
Timing Requirements................................................ 187
Enabling and Disabling ............................................. 156
Operation .................................................................. 156
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