STR750FXX STMICROELECTRONICS [STMicroelectronics], STR750FXX Datasheet
STR750FXX
Related parts for STR750FXX
STR750FXX Summary of contents
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... Up to 72/38 I/O ports – 72/38 GPIOs with High Sink capabilities – Atomic bit SET and RES operations Table 1. Device summary Reference Root part number STR750Fxx STR750FV0, STR750FV1, STR750FV2 STR751Fxx STR751FR0, STR751FR1, STR751FR2 STR752Fxx STR752FR0, STR752FR1, STR752FR2 STR755FR0, STR755FR1, STR755FR2 STR755Fxx STR755FV0, STR755FV1, STR755FV2 Rev 3 ...
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... Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 2/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx Pin Description Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power Supply Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 I/O characteristics versus the various power schemes (3.3V or 5.0V Current Consumption Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 General operating conditions ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx 5.3.8 5.3.9 5.3.10 5.3.11 5.3.12 6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 TB and TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 62 USB characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Contents 3/81 ...
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... Operating Temp. 3 UARTs, 2 SSPs, 1 I2C, 3 timers 1 PWM timer, Common Peripherals 38 I/Os 13 Wake-up lines, 11 A/D Channels USB/CAN peripherals None Operating Voltage 3. Packages (x) 4/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx STR751FR0/ STR752FR0/ STR751FR1/ STR752FR1/ STR751FR2 STR752FR2 64K/128K/256K 16K RWW -40 to +85°C / -40 to +105°C (see USB CAN 3 ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx 3 Introduction This Datasheet contains the description of the STR750F family features, pinout, Electrical Characteristics, Mechanical Data and Ordering information. For complete information on the Microcontroller memory, registers and peripherals. Please refer to the STR750F Reference Manual. For information on the ARM7TDMI-S core please refer to the ARM7TDMI-S Technical Reference Manual available from Arm Ltd ...
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... Power Scheme 3: Single external 5.0V power source. In this configuration the V supply required for the internal logic is generated internally by the main voltage CORE 6/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx supply is generated internally by the low power voltage BACKUP is provided externally through the V pin. This scheme is intended to save power consumption ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx regulator and the V regulator. This scheme has the advantage of requiring only one 5.0V power source. ● Power Scheme 4: Dual external 5.0V and 1.8V power sources. In this configuration, the internal voltage regulators are switched off, by forcing the VREG_DIS pin to high level. V ...
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... TIM timers which has the same architecture and it can work together with the TIM timers via the Timer Link feature for synchronization or event chaining.The PWM timer is mapped to a DMA channel. 8/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx and detailed in Table 6. This remapping is done by the application via ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx I²C bus The I²C bus interface can operate in multi-master and slave mode. It can support standard and fast modes (up to 400KHz). High Speed Universal Asynch. Receiver Transmitter (UART) The three UART interfaces are able to communicate at speeds Mbit/s. They provide hardware management of the CTS and RTS signals and have LIN Master capability ...
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... Each of the 72 GPIO pins (38 GPIOs in 64-pin devices) can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down Peripheral Alternate Function. Port 1. exception, it can be used as general-purpose input only or wake-up from STANDBY mode (WKP_STDBY). Most of the GPIO pins are shared with digital or analog alternate functions. 10/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx 3.2 Block Diagram Figure 1. STR750 block diagram BOOT1, BOOT0 as AF TEST NJTRST JTDI JTCK JTMS JTDO as AF SCLK, MOSI MISO 15AF P0[31:0] P1[19:0] P2[19:0] 16AF VDDA_ADC VSSA_ADC 2xICAP, 2xOCMP as AF 2xICAP, 2xOCMP as AF 2xICAP, 2xOCMP as AF PWM1, PWM1N ...
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... ADC_IN13 / P1.12 ADC_IN0 / TIM2_OC1/ P0.02 MCO / TIM0_TI1 / P0.01 BOOT0 / TIM0_OC1 / P0.00 TIM1_TI2 / P0.31 TIM1_OC2 / P0.30 ADC_IN8 / TIM1_TI1 / P0.29 TIM1_OC1 / P0.28 ADC_IN6 / UART1_RTS / P0.23 TIM2_OC1/ P2.04 UART1_RTS / P2.03 ADC_IN5 / UART1_CTS / P0.22 UART1_TX / P0.21 UART1_RX / P0.20 UART0_RTS / RTCK / P0. A/D input channels = 15 External interrupts / Wake-up Lines 12/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx TEST SS_IO 11 LQFP100 ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx Figure 3. LQFP64 Pinout ADC_IN0 / TIM2_OC1 / P0.02 MCO / TIM0_TI1 / P0.01 BOOT0 / TIM0_OC1 / P0.00 ADC_IN8 / TIM1_TI1 / P0.29 UART2_TX / UART0_RTS / RTCK / P0. A/D input channels = 13 External interrupts / Wake-up Lines ADC_IN13 / P1. TIM1_OC1 / P0.28 6 TEST SS_IO_4 LQFP64 UART1_TX / P0.21 9 UART1_RX / P0 ...
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... LFBGA100 ball connections P0.03 P1.13 P1.14 B P1.12 P0.02 P0.01 C P0.31 P0. P0.29 P0. P0.28 P0.23 P0.22 F P2.03 P0.21 P0.20 G NJTRST P1.18 P1.19 H P0.13 P1.16 P1.17 J P0.11 P0.12 P1.11 K P0.10 P0.09 P0.08 Table 5. LFBGA64 ball connections 1 A P0.03 B P1.12 C P0.01 D P0.29 E P1.18 F P0.13 G P0.11 H P0.10 14/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx P1.04 P1.06 P1.08 P1.05 P1.07 P1.09 V P1.10 P2.09 DD_IO 18 V P1.01 P1.15 SS_IO SS18 V TEST P1.00 NRSTOUT VREG_DIS NRSTIN SS_IO P2.02 P2.04 P2.05 P2.01 P2.00 P2.07 P2.19 P2.18 P2.17 P0.27 P0.19 P0.26 P0.18 P0.17 P0. P1.04 P1.06 SS_IO V P1.05 P1.07 DD_IO P0.02 P0. P0.28 TEST V SS_IO P1.19 P0.20 P0.21 NJTRST P1.16 P1.17 P0.12 P1.11 P0.19 P0.09 P0 ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx 4.0.1 Pin Description Table Legend / Abbreviations for Type: Input Levels: Inputs: Outputs: External Interrupts/wake-up lines: EITx Table input output supply, All Inputs are LVTTL at V ± 0.5V. In both cases, T DD_IO V =0.8V V =2.0V ILmax IHmin All inputs can be configured as floating or with ...
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... Pin Name P1. ADC_IN13 P0. TIM2_OC1 / ADC_IN0 P0.01 / TIM0_TI1 MCO P0. TIM0_OC1 / BOOT0 5 C1 P0.31 / TIM1_TI2 P0. TIM1_OC2 16/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx Input Output OD (3) I EIT12 I EIT0 I I ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx Table 6. STR750F pin description (continued) Pin n° Pin Name P0.29 / TIM1_TI1 ADC_IN8 P0. TIM1_OC1 TEST VSS_IO P0. UART1_RTS / ADC_IN6 P2. TIM2_OC1 P2. UART1_RTS 14 F4 P2.02 P0. UART1_CTS / ADC_IN5 P0. UART1_TX P0. ...
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... ADC_IN7 P0. UART2_CTS P0. UART2_TX P0. UART2_RX P0.19 / USB_CK / SSP1_NSS / ADC_IN4 P0. SSP1_MOSI P0. SSP1_MISO / ADC_IN3 P0. SSP1_SCLK 18/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx Input Output OD ( EIT4 I I/O T ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx Table 6. STR750F pin description (continued) Pin n° Pin Name 43 H9 P2. VDD_IO VDDA_PLL XT2 XT1 48 J10 31 G6 VSS_IO 49 K10 32 G8 VSSA_PLL 50 J8 P2. P2. V18REG VSS18 54 F9 ...
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... P2.09 / PWM1N 83 G7 P2.08 / PWM2 84 G6 P2.07 / PWM2N 85 F7 P2.06 / PWM3 86 F6 P2.05 / PWM3N P1.08 / PWM1N / ADC_IN11 P1.07 / PWM2 P1.06 / PWM2N / ADC_IN10 P1.05 / PWM3 20/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx Input Output OD ( ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx Table 6. STR750F pin description (continued) Pin n° Pin Name P1.04 / PWM3N / ADC_IN9 P1. ADC_IN15 P1. ADC_IN14 94 D5 P1.01 / TIM0_TI2 P1. TIM0_OC2 V18 VSS18 VSS_IO VDD_IO P0.03 / TIM2_TI1 100 ADC_IN1 1 ...
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... Pin Description Figure 4. Required external capacitors when regulators are used 97 V SS18 SS18 LFBGA100 22/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx 18BKP 18 1µF V SSBKP 54 LQFP100 V SS18 53 10 µF V 18REG 52 V DD_IO 44 1 µ 18BKP 18 1µF ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx 4.1 Memory map Figure 5. Memory map Addressable Memory Space 4 Gbytes 0xFFFF FFFF APB TO ARM7 BRIDGE 0xFFFF 8000 7 0xE000 0000 0xDFFF FFFF 6 0xC000 0000 0xBFFF FFFF 5 0xA000 0000 0x9FFF FFFF 4 0x9000 0013 SMI Registers 0x9000 0000 0x83FF FFFF SMI Ext. Memory ...
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... Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 24/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx . SS max (given by the selected A =25° DD_IO =1 ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 6. Pin loading conditions 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 7. Pin input voltage STR7 PIN C =50pF L STR7 PIN ...
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... V SS18 V 18REG 10µF V SS18 V DD_IO 1µF 3.3V +/-0.3V V SS_IO GP I/Os V DD_PLL V SS_PLL V DD_ADC V SS_ADC ADC IN 26/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx IN STANDBY MODE THIS BLOCK IS KEPT POWERED ON LOW POWER V ~1.4V LPVREG VOLTAGE REGULATOR V 18 MAIN V = 1.8V MVREG VOLTAGE REGULATOR V =3.3V IO OUT I/O LOGIC IN 3.3V PLL 3.3V ADC BACKUP V CIRCUITRY ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx Power supply scheme 2: Dual external 1.8V and 3.3V supply Figure 9. Power supply scheme 2 V 18_BKP V SS_BKP V DD_IO VREG_DIS 18REG 1.8V V SS18 V DD_IO 3.3V +/-0.3V V SS_IO GP I/Os V DD_PLL V SS_PLL V DD_ADC V SS_ADC ADC IN OFF LOW POWER V LPVREG VOLTAGE REGULATOR OFF MAIN V VOLTAGE MVREG ...
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... V SS18 V 18REG 10µF V SS18 V DD_IO 1µF 5.0V +/-0.5V V SS_IO GP I/Os V DD_PLL V SS_PLL V DD_ADC V SS_ADC ADC IN 28/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx IN STANDBY MODE THIS BLOCK IS KEPT POWERED ON LOW POWER V ~1.4V LPVREG VOLTAGE REGULATOR V 18 MAIN V = 1.8V MVREG VOLTAGE REGULATOR V =5.0V IO OUT I/O LOGIC IN 5.0V PLL 5.0V ADC BACKUP V CIRCUITRY ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx Power supply scheme 4: Dual external 1.8 V and 5.0 V supply Figure 11. Power supply scheme 4 V 18_BKP V SS_BKP V DD_IO VREG_DIS 18REG 1.8V V SS18 V DD_IO 5.0V +/-0.5V V SS_IO GP I/Os V DD_PLL V SS_PLL V DD_ADC V SS_ADC ADC IN 5.1.7 I/O characteristics versus the various power schemes (3.3V or 5.0V) Unless otherwise mentioned, all the I/O characteristics are valid for both ● ...
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... I DD DDA_PLL DDA_ADC Figure 13. Power consumption measurements in power scheme 2 (regulators disabled) 3.3V Supply I and I are measured which correspond to: DD_v33 DD_v18 DD_v33 DDA_PLL DD_v18 18 30/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx V DDA_ADC V DDA_PLL V DD_IO pins (including DDA_ADC V DDA_PLL V DD_IO I DD_v33 ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx Figure 14. Power consumption measurements in power scheme 3 (regulators enabled) 5.0V Supply I is measured, which corresponds to the total current consumption : DDA_PLL DDA_ADC Figure 15. Power consumption measurements in power scheme 4 (regulators disabled) 5.0V Supply I and I are measured which correspond to: DD_v50 DD_v18 ...
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... V there is no positive injection current, and the corresponding V 3. Only when using external 1.8 V power supply. All the power ( pins must always be connected to the external 1.8 V supply. SSBKP 32/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx Ratings Including V and V DDA_ADC DDA_PLL Digital 1.8 V Supply voltage on all V power pins (when 1 ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx 5.2.2 Current characteristics Table 8. Current characteristics Symbol (1) I VDD_IO (1) I VSS_IO I IO (3) & (4) I INJ(PIN) ΣI (3) INJ(PIN) 1. The user can use GPIOs to source or sink high current ( for O8 type High Sink I/Os). In this case, the user must ensure that these absolute max. values are not exceeded (taking into account the ...
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... Symbol Parameter t V VDD_IO DD_IO t V rise time rate V18 18 1. Data guaranteed by characterization, not tested in production. 34/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx DD_IO Parameter Accessing SRAM with 0 wait states Accessing Flash in burst mode, ≤85° Accessing Flash in burst mode >85° ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx 5.3.3 Embedded voltage regulators Subject to general operating conditions for V Table 12. Embedded voltage regulators Symbol V MVREG V LPVREG (1) t VREG_PWRUP observed on the V MVREG - In STOP mode with MVREG OFF (LP_PARAM13 bit). See note STANDBY mode. See note STANDBY mode STOP mode ...
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... The conditions for these consumption measurements are described at the beginning of 2. Typical data are based Data based on product characterisation, tested in production at V supply mode or regulator output value in single supply mode) and T 36/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx Figure 12 on page 30 , and T DD_IO Table 13 ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx Table 14. Maximum power consumption in STOP and STANDBY modes Symbol Parameter LP_PARAM bits: ALL OFF Single supply scheme see LP_PARAM bits: ALL OFF Supply Dual supply scheme see current in LP_PARAM bits: ALL OFF STOP mode Single supply scheme see ...
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... Temp (°C) Figure 18. Power consumption in STANDBY mode (3.3 V range) 30 TYP (3.3V) 25 MAX (3.6V -40 25 Temp (°C) 38/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx Figure 17. Power consumption in STOP mode 350 300 250 200 150 100 105 -40 Figure 19. Power consumption in STANDBY ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx Typical power consumption The following measurement conditions apply to In RUN mode: ● Program is executed from Flash (except if especially mentioned). The program consists of an infinite loop. When f ● A standard 4 MHz crystal source is used. ● In all cases the PLL is used to multiply the frequency. ...
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... The conditions for these consumption measurements are described at the beginning of 4. Single supply scheme see Figure 5. Parameter setting BURST=1, WFI_FLASHEN=1 6. Parameter setting BURST=0, WFI_FLASHEN=0 7. Parameter setting WFI_FLASHEN=0, OSC4MOFF=1 40/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx DD_IO Conditions =60 MHz, f =30 MHz PCLK =56 MHz, f =28 MHz ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx Table 16. Dual supply supply typical power consumption in Run, WFI, Slow and Slow-WFI modes To calculate the power consumption in Dual supply mode, refer to the values given in consider that this consumption is split as follows DD(single supply) DD(dual supply) For 3.3V range: I ...
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... DD(MVREG) (LP_PARAM bit: MVREG ON) Low Power Voltage Regulator + RSM I DD(LPVREG) current static current consumption 1. Measurements performed in 3.3V single supply mode see 42/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx power consumption (1) Conditions External components specified 4/8 MHz Crystal / Ceramic Resonator Oscillator (XT1/XT2) on page 46 STOP mode includes leakage where V is internally set to 1 ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx On-Chip peripheral power consumption Conditions: – DD_IO – 25° – Clocked by OSC4M with PLL multiplication =32 MHz PCLK . Table 19. On-Chip peripherals Symbol I TIM Timer supply current DD(TIM) I PWM Timer supply current DD(PWM) I SSP supply current ...
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... L 1. Data based on typical application software. 2. Time measured between interrupt event and interrupt vector fetch. ∆t needed to finish the current instruction execution. 3. Data based on design simulation and/or technology characteristics, not tested in production. 44/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx DD_IO Parameter Conditions see Figure 20 ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx XRTC1 external Clock source Subject to general operating conditions for V Table 21. XRTC1 external Clock source Symbol External clock source f XRTC1 frequency XRTC1 input pin high V XRTC1H level voltage XRTC1 input pin low level V XRTC1L voltage t w(XRTC1H) XRTC1 high or low time ...
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... This value is measured for a standard crystal resonator and it can vary significantly with the crystal/ceramic resonator manufacturer. Figure 21. Typical application with MHz crystal or ceramic resonator WHEN RESONATOR WITH INTEGRATED CAPACITORS 46/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx Conditions 4 MHz Crystal/Resonator Oscillator connected on XT1/XT2 XTDIV MHz Crystal/Resonator Oscillator ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx OSC32K crystal / ceramic resonator oscillator The STR7 RTC clock can be supplied with a 32.768 kHz Crystal/Ceramic resonator oscillator. All the information given in this paragraph are based on product characterisation with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time ...
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... N. See Figure 24 Figure 23. Self-referred jitter (single and long term) IDEAL CK_PLL ACTUAL CK_PLL Figure 24. Cycle-to-cycle jitter IDEAL CK_PLL ACTUAL CK_PLL 48/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx n n+1 T single period trigger point jitter n n+1 T Tcycle 1 Tcycle 2 is the minimum time min --- ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx PLL characteristics Subject to general operating conditions for V Table 24. PLL characteristics Symbol PLL input clock f PLL_IN PLL input clock duty cycle f PLL multiplier output clock PLL_OUT f VCO frequency range VCO t PLL lock time LOCK Single period jitter (+/-3Σ peak ∆ ...
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... Endurance (Bank 1 sectors) END_B1 Y Data Retention RET t Erase Suspend Rate ESR 1. Data based on characterisation not tested in production. 50/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx DD_IO Parameter Test Conditions Single Word programming of a checker-board pattern Single Word programming of a checker-board pattern Not preprogrammed (all 1) Preprogrammed (all 0) ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx 5.3.7 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs). ● ...
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... Body Model) Electro-static discharge voltage V ESD(MM) (Machine Model) Electro-static discharge voltage V ESD(CDM) (Charge Device Model) 1. Data based on product characterisation, not tested in production. 52/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx Monitored Conditions Frequency Band Flash devices: 0.1 MHz to 30 MHz =3 DD_IO 30 MHz to 130 MHz =+25° C, ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx Static and dynamic latch-up ● LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample ...
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... The R pull-up and generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external interrupt source. 54/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx DD_IO I/O static characteristics Parameter TTL ports (1) See Section 5.3.12 on page 72 (3) ≤ ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx Figure 25. Connecting unused I/O pins Output driving current The GP I/Os have different drive capabilities: ● O2 outputs can sink or source up to +/-2 mA. ● O4 outputs can sink or source up to +/-4 mA. ● outputs can sink or source up to +/- can sink +20 mA (with a relaxed V ...
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... The I current sourced must always respect the absolute maximum rating specified in IO the sum of I (I/O ports and control pins) must not exceed I IO 56/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx I/O Output Drive characteristics for V = 3.0 to 3.6 V and EN33 bit =1 DD_IO 4.5 to 5.5 V and EN33 bit =0 ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx Output speed Subject to general operating conditions for V Table 34. Output speed I/O Symbol Type f max(IO)out t f(IO)out O2 t r(IO)out f max(IO)out t f(IO)out O4 t r(IO)out f max(IO)out t f(IO)out O8 t r(IO)out 1. The maximum frequency is defined as described in 2. Data based on product characterisation, not tested in production. ...
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... This means that all spikes with a maximum duration of 150 ns with minimum interval between spikes are filtered. Data guaranteed by design, not tested in production. 58/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx (see : General characteristics on page PU : General characteristics on page ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx Figure 27. Recommended NRSTIN pin protection EXTERNAL RESET CIRCUIT 1. The user must ensure that the level on the NRSTIN pin can go below the V NRSTIN and NRSTOUT pins on page V DD_IO R PU NRSTOUT TO RESET OTHER CHIPS V DD_IO R PU NRSTIN Filter 0.01µF 58 ...
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... COUNTER is selected (16-bit Prescaler) Maximum t Possible MAX_COUNT Count 1. Take into account the frequency limitation due to the I/O speed capability when outputting the PWM to I/O pin, described in 60/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx DD_IO Conditions TIM0,1 CK_TIM(MAX CK_TIM CK_SYS 60 MHz ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx Table 37. PWM Timer (PWM) Symbol t PWM resolution time res(PWM) Res PWM resolution PWM PWM/DAC output step ( voltage Timer clock period t when internal clock is COUNTER selected Maximum Possible t MAX_COUNT Count 1. Take into account the frequency limitation due to the I/O speed capability when outputting the PWM to an ...
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... Data input (MISO) hold time t h w.r.t SCK sampling edge 1. Data based on characterisation results, not tested in production. 2. Max frequency for the 2 SSPs is f limitation due to I/O speed capability. SSP0 uses IO4 type while SSP1 uses IO2 type I/Os. 62/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx , 3.0V to 3.3V, V18 =1.8V (1) Parameter Conditions SSP0 (2) ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx Figure 28. SPI configuration - Master Mode, Single Transfer NSS OUTPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 MISO DONT CARE INPUT t NSSLQV MOSI OUTPUT Figure 29. SPI Configuration - Master Mode, Continous Transfer, CPHA=0 NSS OUTPUT CPOL=0 CPOL=1 MOSI ...
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... INPUT MOSI OUTPUT Figure 32. TI configuration - master mode, continous transfer NSS OUTPUT trigger sample SCK OUTPUT MOSI OUTPUT DONT CARE MISO INPUT 64/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx t c(SCK) trigger trigger sample sample edge edge edge edge t t w(SCKH) w(SCKL f(SCK) ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx SSP Synchronous Serial Peripheral in Slave mode (SPI or TI mode) Subject to general operating conditions with C Table 39. SSP Slave mode characteristics Symbol f SPI clock frequency SCK NSS input setup time w.r.t t su(NSS) SCK first edge NSS input hold time w.r.t t h(NSS) ...
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... MOSI INPUT Figure 36. SPI configuration - slave mode with CPHA=1, continous transfer NSS OUTPUT CPOL=0 CPOL MOSI OUTPUT DONT CARE MISO INPUT 66/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx c(SCK) sample trigger sample trigger sample trigger sample t NSSLQV z MSB OUT MSB IN FRAME 1 t su(NSS) ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx Figure 37. TI configuration - slave mode, single transfer NSS INPUT t SCK INPUT MOSI DONT CARE INPUT MISO z OUTPUT Figure 38. TI configuration - slave mode, continous transfer NSS OUTPUT trigger sample SCK OUTPUT DONT CARE MOSI INPUT MISO OUTPUT ...
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... Restriction: The I/O pins which SDA and SCL are mapped to are not “True” Open- Drain: when configured as open-drain, the PMOS connected between the I/O pin and V is disabled, but it is still present. Also, there is a protection diode between the DD_IO I/O pin and V 68/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx ≈ L (1) Parameter Conditions / MHz. ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx not possible to power off the STR7x while some another I powered on: otherwise, the STR7x will be powered by the protection diode. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 41. SDA and SCL characteristics ...
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... Figure 41. USB: data signal rise and fall time Differential Data Lines V CRS V SS Table 44. USB: Full speed electrical characteristics Symbol 70/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx Parameter USB transceiver startup time USB DC Electrical Characteristics Parameter Input Levels Includes V Range Threshold Output Levels ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx Table 44. USB: Full speed electrical characteristics Symbol t Rise/ Fall Time matching rfm V Output signal Crossover Voltage CRS 1. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). Parameter Conditions ...
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... PCB (dependent on soldering and PCB layout quality) plus PARASITIC the pad capacitance (3 pF). A high C f should be reduced. ADC 4. Depending on the input signal variation (f allow the use of a larger serial resistor (R 72/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx DDA_ADC Parameter Conditions (2) (3)(4) +400 µA injected on any pin -400 µA injected ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx ADC Accuracy vs. Negative Injection Current Injecting negative current on specific pins listed in input pin being converted) should be avoided as this significantly reduces the accuracy of the conversion being performed recommended to add a Schottky diode (pin to ground) to pins which may potentially inject negative current. ...
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... A/D input being converted. Software Filtering of Spurious Conversion Results For EMC performance reasons recommended to filter A/D conversion outliers using software filtering techniques. Figure 43. Power supply filtering 74/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx is used as a reference voltage by the A/D converter and DDA_ADC 1 to 10µF 0.1µF STR7 ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx Table 47. ADC accuracy ADC Accuracy with f This assumes that the ADC is calibrated Symbol |E | Total unadjusted error Offset error O E Gain Error Differential linearity error Integral linearity error L 1. Calibration is needed once after each power-up. ...
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... Package characteristics 6 Package characteristics 6.1 Package mechanical data Figure 45. 64-Pin Low Profile Quad Flat Package (10x10) Figure 46. 100-Pin Low Profile Flat Package (14x14) 76/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx inches Dim. Min Typ Max Min ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx Figure 47. 64-Low Profile Fine Pitch Ball Grid Array Package Figure 48. 100-Low Profile Fine Pitch Ball Grid Array Package Figure 49. Recommended PCB design rules (0.80/0.75mm pitch BGA) Dpad Dsm Solder paste – Non solder mask defined pads are recommended – ...
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... LQFP 0.5 mm pitch Thermal Resistance Junction-Ambient Θ JA LFBGA 1.7mm Thermal Resistance Junction-Ambient Θ JA LFBGA 100 - 1.7mm 78/81 STR750Fxx STR751Fxx STR752Fxx STR755Fxx must never exceed 125° degrees Celsius, may be calculated using the J )(1) JA and ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx 7 Order codes Table 49. Order codes Partnumber STR750FV0T6 STR750FV1T6 STR750FV2T6 STR750FV2H6 STR751FR0T6 STR751FR1T6 STR751FR2T6 STR751FR2H6 STR752FR0T6 STR752FR1T6 STR752FR2T6 STR752FR2H6 STR752FR0T7 STR752FR1T7 STR752FR2T7 STR752FR2H7 STR755FR0T6 STR755FR1T6 STR755FR2T6 STR755FR2H6 STR755FV0T6 STR755FV1T6 STR755FV2T6 STR755FV2H6 1. For other memory sizes, contact sales office. ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx Description of Changes 1 Initial release 2 Added power consumption data for 5V operation in Changed datasheet title from STR750F to STR750FXX STR751Fxx STR752Fxx STR755xx. Added Table 1: Device summary on page 1 Added note 1 to Table 6 Added STOP mode IDD max. values in Updated XT2 driving current in ...
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... STR750Fxx STR751Fxx STR752Fxx STR755Fxx Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...