MC9S08AW8A FREESCALE [Freescale Semiconductor, Inc], MC9S08AW8A Datasheet - Page 69
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MC9S08AW8A
Manufacturer Part Number
MC9S08AW8A
Description
8-Bit HCS08 Central Processor Unit (CPU)
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S08AW8A.pdf
(344 pages)
- Current page: 69 of 344
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5.6
The MC9S08AC16 Series includes a system to protect against low voltage conditions in order to protect
memory contents and control MCU system states during supply voltage variations. The system is
comprised of a power-on reset (POR) circuit and an LVD circuit with a user selectable trip voltage, either
high (V
voltage is selected by LVDV in SPMSC2. The LVD is disabled upon entering any of the stop modes unless
the LVDSE bit is set. If LVDSE and LVDE are both set, then the MCU cannot enter stop2, and the current
consumption in stop3 with the LVD enabled will be greater.
5.6.1
When power is initially applied to the MCU, or when the supply voltage drops below the V
POR circuit will cause a reset condition. As the supply voltage rises, the LVD circuit will hold the chip in
reset until the supply has risen above the V
following a POR.
5.6.2
The LVD can be configured to generate a reset upon detection of a low voltage condition by setting
LVDRE to 1. After an LVD reset has occurred, the LVD system will hold the MCU in reset until the supply
voltage has risen above the level determined by LVDV. The LVD bit in the SRS register is set following
either an LVD reset or POR.
5.6.3
When a low voltage condition is detected and the LVD circuit is configured for interrupt operation (LVDE
set, LVDIE set, and LVDRE clear), then LVDF will be set and an LVD interrupt will occur.
5.6.4
The LVD system has a low voltage warning flag to indicate to the user that the supply voltage is
approaching, but is still above, the LVD voltage. The LVW does not have an interrupt associated with it.
There are two user selectable trip voltages for the LVW, one high (V
voltage is selected by LVWV in SPMSC2. Setting the LVW trip voltage equal to the LVD trip voltage is
not recommended. Typical use of the LVW would be to select V
5.7
The real-time interrupt function can be used to generate periodic interrupts. The RTI can accept two
sources of clocks, the 1-kHz internal clock or an external clock if available. The 1-kHz internal clock
source is completely independent of any bus clock source and is used only by the RTI module and, on some
MCUs, the COP watchdog. To use an external clock source, it must be available and active. The RTICLKS
bit in SRTISC is used to select the RTI clock source.
Freescale Semiconductor
LVDH
Low-Voltage Detect (LVD) System
Real-Time Interrupt (RTI)
Power-On Reset Operation
LVD Reset Operation
LVD Interrupt Operation
Low-Voltage Warning (LVW)
) or low (V
LVDL
). The LVD circuit is enabled when LVDE in SPMSC1 is high and the trip
MC9S08AC16 Series Data Sheet, Rev. 6
LVDL
level. Both the POR bit and the LVD bit in SRS are set
Chapter 5 Resets, Interrupts, and System Configuration
LVWH
LVWH
and V
) and one low (V
LVDL
.
LVWL
POR
). The trip
level, the
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