LM3S600-IQC20-A0T BOOKHAM [Bookham, Inc.], LM3S600-IQC20-A0T Datasheet - Page 129
LM3S600-IQC20-A0T
Manufacturer Part Number
LM3S600-IQC20-A0T
Description
Microcontroller
Manufacturer
BOOKHAM [Bookham, Inc.]
Datasheet
1.LM3S600-IQC20-A0T.pdf
(378 pages)
- Current page: 129 of 378
- Download datasheet (4Mb)
GPIO Interrupt Both Edges (GPIOIBE)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
Offset 0x408
Type R/W, reset 0x0000.0000
October 01, 2007
Reset
Reset
Type
Type
Bit/Field
31:8
7:0
RO
RO
31
15
0
0
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408
The GPIOIBE register is the interrupt both-edges register. When the corresponding bit in the GPIO
Interrupt Sense (GPIOIS) register (see page 128) is set to detect edges, bits set to High in GPIOIBE
configure the corresponding pin to detect both rising and falling edges, regardless of the
corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 130). Clearing a bit
configures the pin to be controlled by GPIOIEV. All bits are cleared by a reset.
RO
RO
30
14
0
0
reserved
Name
IBE
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
RO
RO
Type
27
11
R/W
0
0
RO
RO
RO
26
10
0
0
Reset
0x00
0x00
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Interrupt Both Edges
The IBE values are defined as follows:
RO
RO
Value
24
0
8
0
reserved
0
1
Description
Interrupt generation is controlled by the GPIO Interrupt Event
(GPIOIEV) register (see page 130).
Both edges on the corresponding pin trigger an interrupt.
Note:
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
Single edge is determined by the corresponding bit
in GPIOIEV.
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
IBE
LM3S600 Microcontroller
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
R/W
RO
17
0
1
0
R/W
RO
16
0
0
0
129
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