LM3S600-IQC20-A0T BOOKHAM [Bookham, Inc.], LM3S600-IQC20-A0T Datasheet - Page 54
LM3S600-IQC20-A0T
Manufacturer Part Number
LM3S600-IQC20-A0T
Description
Microcontroller
Manufacturer
BOOKHAM [Bookham, Inc.]
Datasheet
1.LM3S600-IQC20-A0T.pdf
(378 pages)
- Current page: 54 of 378
- Download datasheet (4Mb)
System Control
6.1.5
6.2
54
determine the course of action to take. The actual failure indication and clock switching does not
clear without a write to the CLKVCLR register, an external reset, or a POR reset. The clock
verification timers are controlled by the PLLVER , IOSCVER , and MOSCVER bits in the RCC register.
System Control
For power-savings purposes, the RCGCn , SCGCn , and DCGCn registers control the clock gating
logic for each peripheral or block in the system while the controller is in Run, Sleep, and Deep-Sleep
mode, respectively. The DC1 , DC2 and DC4 registers act as a write mask for the RCGCn , SCGCn,
and DCGCn registers.
In Run mode, the controller is actively executing code. In Sleep mode, the clocking of the device is
unchanged but the controller no longer executes code (and is no longer clocked). In Deep-Sleep
mode, the clocking of the device may change (depending on the Run mode clock configuration)
and the controller no longer executes code (and is no longer clocked). An interrupt returns the device
to Run mode from one of the sleep modes. Each mode is described in more detail in this section.
There are four levels of operation for the device defined as:
■
■
■
Initialization and Configuration
The PLL is configured using direct register writes to the RCC register. The steps required to
successfully change the PLL-based system clock are:
Run Mode. Run mode provides normal operation of the processor and all of the peripherals that
are currently enabled by the RCGCn registers. The system clock can be any of the available
clock sources including the PLL.
Sleep Mode. Sleep mode is entered by the Cortex-M3 core executing a WFI (Wait for
Interrupt) instruction. Any properly configured interrupt event in the system will bring the
processor back into Run mode. See the system control NVIC section of the ARM® Cortex™-M3
Technical Reference Manual for more details.
In Sleep mode, the Cortex-M3 processor core and the memory subsystem are not clocked.
Peripherals are clocked that are enabled in the SCGCn register when auto-clock gating is enabled
(see the RCC register) or the RCGCn register when the auto-clock gating is disabled. The system
clock has the same source and frequency as that during Run mode.
Deep-Sleep Mode. Deep-Sleep mode is entered by first writing the Deep Sleep Enable bit in
the ARM Cortex-M3 NVIC system control register and then executing a WFI instruction. Any
properly configured interrupt event in the system will bring the processor back into Run mode.
See the system control NVIC section of the ARM® Cortex™-M3 Technical Reference Manual
for more details.
The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are
clocked that are enabled in the DCGCn register when auto-clock gating is enabled (see the RCC
register) or the RCGCn register when auto-clock gating is disabled. The system clock source is
the main oscillator by default or the internal oscillator specified in the DSLPCLKCFG register if
one is enabled. When the DSLPCLKCFG register is used, the internal oscillator is powered up,
if necessary, and the main oscillator is powered down. If the PLL is running at the time of the
WFI instruction, hardware will power the PLL down and override the SYSDIV field of the active
RCC register to be /16 or /64, respectively. When the Deep-Sleep exit event occurs, hardware
brings the system clock back to the source and frequency it had at the onset of Deep-Sleep
mode before enabling the clocks that had been stopped during the Deep-Sleep duration.
Preliminary
October 01, 2007
Related parts for LM3S600-IQC20-A0T
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Microcontroller
Manufacturer:
Bookham Technology, Inc.
Datasheet:
Part Number:
Description:
Microcontroller
Manufacturer:
Bookham Technology, Inc.
Datasheet:
Part Number:
Description:
10Gb/s surface mount coplanar PIN preamp receiver with integrated MEMS VOA
Manufacturer:
BOOKHAM [Bookham, Inc.]
Datasheet:
Part Number:
Description:
40W 806nm 30% Fill Factor High Power Laser Diode Bar on Microchannel Cooler
Manufacturer:
BOOKHAM [Bookham, Inc.]
Datasheet:
Part Number:
Description:
50W 806nm High Power Laser Diode Bar on Microchannel Cooler
Manufacturer:
BOOKHAM [Bookham, Inc.]
Datasheet:
Part Number:
Description:
80W 9xxnm High Power Laser Diode Bar on Microchannel Cooler
Manufacturer:
BOOKHAM [Bookham, Inc.]
Datasheet:
Part Number:
Description:
110W 10xxnm High Power Laser Diode Bar on Microchannel Cooler
Manufacturer:
BOOKHAM [Bookham, Inc.]
Datasheet:
Part Number:
Description:
10gb/s Surface Mount Coplanar Pin Preamp Receiver With Integrated Mems Voa
Manufacturer:
Bookham, Inc.
Datasheet:
Part Number:
Description:
10Gb/s DWDM EA Modulator and DFB Laser with GPO RF Connector
Manufacturer:
Bookham Technology, Inc.
Part Number:
Description:
10Gb/s DWDM EA Modulator and DFB Laser with GPO RF Connector
Manufacturer:
Bookham Technology, Inc.
Part Number:
Description:
10Gb/s DWDM EA Modulator and DFB Laser with GPO RF Connector
Manufacturer:
Bookham Technology, Inc.
Part Number:
Description:
10Gb/s EA Modulator and DFB Laser with GPO RF Connector
Manufacturer:
Bookham Technology, Inc.
Datasheet:
Part Number:
Description:
10Gb/s EA Modulator and DFB Laser with GPO RF Connector
Manufacturer:
Bookham Technology, Inc.
Datasheet:
Part Number:
Description:
10Gb/s DWDM EA Modulator and DFB Laser with GPO RF Connector
Manufacturer:
Bookham Technology, Inc.
Part Number:
Description:
40 Channel Mux/Demux with 100GHz Channels
Manufacturer:
Bookham Technology, Inc.