M38867E8AHP MITSUBISHI [Mitsubishi Electric Semiconductor], M38867E8AHP Datasheet - Page 42

• Manufacturer Part Number: M38867E8AHP
• Description: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER??
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

[I
The I
control, S
•Bits 0 to 4: S
These bits control the S
•Bit 5: S
This bit specifies the S
standard clock mode is selected. When the bit is set to “1,” the
high-speed clock mode is selected.
When connecting the bus of the high-speed mode I
dard (maximum 400 kbits/s), use 8 MHz or more oscillation
frequency f(X
•Bit 6: ACK bit (ACK BIT)
This bit sets the S
When this bit is set to “0,” the ACK return mode is selected and
S
set to “1,” the ACK non-return mode is selected. The S
the “H” status at the occurrence of an ACK clock.
However, when the slave address agree with the address data in
the reception of address data at ACK BIT = “0,” the S
matically made “L” (ACK is returned). If there is a disagreement
between the slave address and the address data, the S
matically made “H” (ACK is not returned).
•Bit 7: ACK clock bit (ACK)
This bit specifies the mode of acknowledgment which is an ac-
knowledgment response of data transfer. When this bit is set to
“0,” the no ACK clock mode is selected. In this case, no ACK clock
occurs after data transmission. When the bit is set to “1,” the ACK
clock mode is selected and the master generates an ACK clock
each completion of each 1-byte data transfer. The device for
transmitting address data and control data releases the S
occurrence of an ACK clock (makes S
ACK bit generated by the data receiving device.
Note: Do not write data into the I
42
ACK clock: Clock for acknowledgment
DA
2
C Clock Control Register (S2)] 0016
goes to “L” at the occurrence of an ACK clock. When the bit is
2
data is written during transfer, the I
that data cannot be transferred normally.
C clock control register (address 0016
CL
CL
mode specification bit (FAST MODE)
mode and S
IN
CL
) and high-speed mode (2 division main clock).
frequency control bits (CCR0–CCR4)
DA
status when an ACK clock is generated.
CL
CL
CL
frequency. Refer to Table 10.
mode. When this bit is set to “0,” the
frequency.
2
C clock control register during transfer. If
2
C clock generator is reset, so
DA
“H”) and receives the
16
) is used to set ACK
2
C bus stan-
DA
16
DA
DA
is held in
DA
is auto-
is auto-
at the
Fig. 37 Structure of I
Table 10 Set values of I
Notes 1: Duty of S
CCR4
0
0
0
0
0
0
0
1
1
1
b 7
A C K
Setting value of
CCR3
2: Each value of S
3: The data formula of S
CCR4–CCR0
0
0
0
0
0
0
0
1
1
1
A C K
B I T
only when the high-speed clock mode is selected and CCR value
= 5 (400 kHz, at
from –4 to +2 cycles of
ates from –2 to +2 cycles of
the case of negative fluctuation, the frequency does not increase
because “L” duration is extended instead of “H” duration reduc-
tion.
These are value when S
nous function is not performed. CCR value is the decimal
notation value of the S
more. When using these setting value, use
Do not set 0 to 2 as CCR value regardless of
Set 100 kHz (max.) in the standard clock mode and 400 kHz
(max.) in the high-speed clock mode to the S
ting the S
/(8
/(4
/(2
frequency
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CCR2
M O D E
F A S T
0
0
0
0
1
1
1
1
1
1
CCR value) Standard clock mode
CCR value) High-speed clock mode (CCR value
CCR value) High-speed clock mode (CCR value = 5)
C C R 4 C C R 3 C C R 2 C C R 1 C C R 0
CCR1
CL
CL
0
0
1
1
0
0
1
0
1
1
clock output is 50 %. The duty becomes 35 to 45 %
frequency control bits CCR4 to CCR0.
MITSUBISHI MICROCOMPUTERS
2
CCR0
C clock control register
CL
0
1
0
1
0
1
0
1
0
1
= 4 MHz). “H” duration of the clock fluctuates
frequency exceeds the limit at
2
CL
C clock control register and S
CL
Setting disabled
Setting disabled
Setting disabled
(at
500/CCR value
Standard clock
CL
frequency is described below:
frequency control bits CCR4 to CCR0.
in the standard clock mode, and fluctu-
– (Note 2)
– (Note 2)
clock synchronization by the synchro-
(Note 3)
b 0
= 4 MHz, unit : kHz) (Note 1)
mode
83.3
17.2
16.6
16.1
100
in the high-speed clock mode. In
I
( S 2 : a d d r e s s 0 0 1 6
S
b i t s
R e f e r t o T a b l e 1 0 .
S
A C K b i t
A C K c l o c k b i t
2
S
C c l o c k c o n t r o l r e g i s t e r
C L
C L
CL
3886 Group
f r e q u e n c y c o n t r o l
m o d e s p e c i f i c a t i o n b i t
0 : S t a n d a r d c l o c k m o d e
1 : H i g h - s p e e d c l o c k
m o d e
0 : A C K i s r e t u r n e d .
1 : A C K i s n o t
r e t u r n e d .
0 : N o A C K c l o c k
1 : A C K c l o c k
frequency
High-speed clock
1000/CCR value
Setting disabled
Setting disabled
Setting disabled
CL
of 4 MHz or less.
400 (Note 3)
frequency.
frequency by set-
(Note 3)
mode
34.5
33.3
32.3
333
250
166
1 6
= 4 MHz or
)
5)
CL