M38867E8AHP MITSUBISHI [Mitsubishi Electric Semiconductor], M38867E8AHP Datasheet - Page 46

• Manufacturer Part Number: M38867E8AHP
• Description: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER??
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

START Condition Generating Method
When writing “1” to the MST, TRX, and BB bits of the I
register (address 0014
address to the I
condition in which the ES0 bit of the I
0015
that, the bit counter becomes “000
put. The START condition generating timing is different in the
standard clock mode and the high-speed clock mode. Refer to
Figure 41, the START condition generating timing diagram, and
Table 11, the START condition generating timing table.
Fig. 41 START condition generating timing diagram
Table 11 START condition generating timing table
Note: Absolute time at
STOP Condition Generating Method
When the ES0 bit of the I
“1,” write “1” to the MST and TRX bits, and write “0” to the BB bit
of the I
STOP condition occurs. The STOP condition generating timing is
different in the standard clock mode and the high-speed clock
mode. Refer to Figure 42, the STOP condition generating timing
diagram, and Table 12, the STOP condition generating timing
table.
Fig. 42 STOP condition generating timing diagram
Table 12 STOP condition generating timing table
Note: Absolute time at
46
I
w r i t e s i g n a l
S
S
Setup
Setup
Item
Hold
Item
Hold
time
time
time
time
2
I
w r i t e s i g n a l
S
S
C s t a t u s r e g i s t e r
C L
D A
2
C L
D A
C s t a t u s r e g i s t e r
16
number of
number of
2
) and the BB flag are “0”, a START condition occurs. After
C status register (address 0014
START/STOP condition
generating selection bit
START/STOP condition
generating selection bit
2
cycles.
cycles.
C data shift register (address 0012
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
= 4 MHz. The value in parentheses denotes the
= 4 MHz. The value in parentheses denotes the
16
) at the same time after writing the slave
2
S e t u p
C control register (address 0015
S e t u p
t i m e
t i m e
13.0 s (52 cycles)
13.0 s (52 cycles)
13.5 s (54 cycles)
13.5 s (54 cycles)
5.0 s (20 cycles)
5.0 s (20 cycles)
5.5 s (22 cycles)
5.5 s (22 cycles)
2
clock mode
clock mode
” and an S
H o l d t i m e
Standard
Standard
H o l d t i m e
2
C control register (address
16
) simultaneously. Then a
CL
for 1 byte is out-
2.5 s (10 cycles)
6.5 s (26 cycles)
2.5 s (10 cycles)
6.5 s (26 cycles)
3.0 s (12 cycles)
7.0 s (28 cycles)
3.0 s (12 cycles)
7.0 s (28 cycles)
High-speed
clock mode
High-speed
clock mode
16
) with the
2
C status
16
) is
START/STOP Condition Detecting Operation
The START/STOP condition detection operations are shown in
Figures 43, 44, and Table 13. The START/STOP condition is set
by the START/STOP condition set bit.
The START/STOP condition can be detected only when the input
signal of the S
lease time, setup time, and hold time (see Table 13).
The BB flag is set to “1” by detecting the START condition and is
reset to “0” by detecting the STOP condition.
The BB flag set/reset timing is different in the standard clock mode
and the high-speed clock mode. Refer to Table 13, the BB flag set/
reset time.
Note: When a STOP condition is detected in the slave mode (MST = 0), an
Fig. 43 START condition detecting timing diagram
Fig. 44 STOP condition detecting timing diagram
Table 13 START condition/STOP condition detecting conditions
Note: Unit : Cycle number of system clock
Setup time
BB flag set/
reset time
S
Hold time
CL
S
S
B B f l a g
release time
interrupt request signal “I
S
S
B B f l a g
SSC value is the decimal notation value of the START/STOP condi-
tion set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC
value. The value in parentheses is an example when the I
STOP condition control register is set to “18
C L
D A
C L
D A
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CL
SSC value –1
SSC value
SSC value + 1 cycle (6.25 s)
SSC value
and S
2
Standard clock mode
2
2
MITSUBISHI MICROCOMPUTERS
S e t u p
S e t u p
S
t i m e
S
t i m e
DA
C L
C L
+ 1 cycle < 4.0 s (3.25 s)
r e l e a s e t i m e
2
cycle < 4.0 s (3.0 s)
pins satisfy three conditions: S
r e l e a s e t i m e
CIRQ” occurs to the CPU.
+ 2 cycles (3.375 s)
H o l d t i m e
H o l d t i m e
B B f l a g
r e s e t
t i m e
B B f l a g
r e s e t
t i m e
3886 Group
16
” at
High-speed clock mode
4 cycles (1.0 s)
2 cycles (1.0 s)
2 cycles (0.5 s)
3.5 cycles (0.875 s)
= 4 MHz.
2
C START/
CL
re-