EP7311-CB-C CIRRUS [Cirrus Logic], EP7311-CB-C Datasheet
EP7311-CB-C
Related parts for EP7311-CB-C
EP7311-CB-C Summary of contents
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... Low-Power System on Chip with SDRAM and Enhanced Digital OVERVIEW The Maverick™ EP7311 is designed for ultra-low-power applications such as PDAs, smart cellular phones, and industrial hand held information appliances. The core- logic functionality of the device is built around an ARM720T processor with four-way set- associative unified cache and a write buffer ...
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... Boot ROM I Package — 208-Pin LQFP — 256-Ball PBGA ® — 204-Ball TFBGA I The fully static EP7311 is optimized for low power dissipation and is fabricated on a 0.25 micron CMOS process I Development Kits — EDB7312: Development Kit with color STN LCD on board. — EDB7312-LW: EDB7312 with Lynuxworks’ ...
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... EP7311 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device the EP7311 is powering, and then deliver the copyrighted information over a secure connection. In addition, secure transactions can benefit by also matching device IDs to server IDs. MaverickKey IDs provide a level of hardware security required for today’ ...
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... Pins are multiplexed. See Table S on page 8 more information. Digital Audio Capability The EP7311 uses its powerful 32-bit RISC processing engine to implement audio decompression algorithms in software. The nature of the on-board RISC processor, and the availability of efficient C-compilers and other software development tools, ensures that a wide range of ...
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... CODEC Interface The EP7311 includes an interface to telephony-type CODECs for easy integration into voice-over-IP and other voice communications systems. The CODEC interface is multiplexed to the same pins as the MCP and SSI2. Pin Mnemonic I/O PCMCLK O Serial bit clock PCMOUT O Serial data out PCMIN I Serial data in ...
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... EINT[3] nEXTFIQ nMEDCHG/nBROM Note: Real-Time Clock The EP7311 contains a 32-bit Real Time Clock (RTC) that can be written to and read from in the same manner as the timer counters. It also contains a 32-bit output match register which can be programmed to generate an interrupt. • Driven by an external 32.768 kHz crystal oscillator ...
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... Internal Boot ROM The internal 128 byte Boot ROM facilitates download of saved code to the on-board SRAM/FLASH. Packaging The EP7311 is available in a 208-pin LQFP package, 256- ball PBGA package or a 204-ball TFBGA package. C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) ...
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... I/O SIBCLK SSITXDA O SIBDOUT SSIRXDA I SIBDIN SSITXFR I/O SIBSYNC SSIRXFR I p/u BUZ O Table R. MCP/SSI2/CODEC Pin Multiplexing 8 The following table shows the pins that have been multiplexed in the EP7311. Signal nMOE nMWE WRITE A[27:15] A[14:13] SSI2 CODEC PD[7:6] SSICLK PCMCLK RUN SSITXDA PCMOUT SSIRXDA PCMIN nMEDCHG SSITXFR PCMSYNC ...
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... EXTERNAL MEMORY- BUFFERS MAPPED EXPANSION BUFFERS ADDITIONAL I/O AND LATCHES Note: A system can only use one of the following peripheral interfaces at any given time: SSI2,CODEC or MCP. DS506PP1 EP7311 completes a low-power system solution. All necessary interface logic is integrated on-chip. MOSCIN DD[0-3] RTCIN nCS[4] PB0 EXPCLK COL[0-7] D[0-31] PA[0-7] ...
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... EP7311 High-Performance, Low-Power System on Chip ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings DC Core, PLL, and RTC Supply Voltage DC I/O Supply Voltage (Pad Ring) DC Pad Input Current Storage Temperature, No Power Recommended Operating Conditions DC core, PLL, and RTC Supply Voltage DC I/O Supply Voltage (Pad Ring) DC Input / Output Voltage ...
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... VIH = V ± 0 VIL = GND ± 0.1 V Both oscillators running, CPU static, Cache enabled, LCD - mA disabled, VIH = GND ± 0.1 V Minimum standby voltage for - V state retention, internal SRAM cache, and RTC operation only EP7311 ± 0.1 V, VIL 11 ...
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... EP7311 High-Performance, Low-Power System on Chip Timings Timing Diagram Conventions This data sheet contains timing diagrams. The following key explains the components used in these diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached unless specifically stated ...
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... CSd t RAa t RAd t RAnv t CAa t CAd t ADv t ADx t MWa t MWd t DAs t DAh t DAd C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) EP7311 Min Typ Max Unit − − − − ...
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... EP7311 High-Performance, Low-Power System on Chip SDRAM Load Mode Register Cycle SDCLK t CSa SDCS t RAa SDRAS t CAa SDCAS t ADv ADDR DATA SDQM t MWa SDMWE Figure 3. SDRAM Load Mode Register Cycle Timing Measurement Note: 1. Timings are shown with CAS latency = 2 2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading. ...
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... CSa t CSd t CAa t CAd t ADv ADCAS t DAs D1 t DAh Figure 4. SDRAM Burst Read Cycle Timing Measurement C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) High-Performance, Low-Power System on Chip DAs DAs DAs DAh DAh DAh EP7311 t RAnv 15 ...
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... EP7311 High-Performance, Low-Power System on Chip SDRAM Burst Write Cycle SDCLK SDCS t RAa SDRAS SDCAS ADDR DATA SDQM SDMWE Note: 1. Timings are shown with CAS latency = 2 2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading. ...
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... Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal DS506PP1 t t CSa CSd t t RAa RAd t CAa Figure 6. SDRAM Refresh Cycle Timing Measurement C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) High-Performance, Low-Power System on Chip t CAd EP7311 17 ...
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... EP7311 High-Performance, Low-Power System on Chip Static Memory Figure 7 through Figure 10 define the timings associated with all phases of the Static Memory. The following table contains the values for the timings of each of the Static Memory modes. Parameter EXPCLK rising edge to nCS assert delay time ...
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... EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity. 2. Address, Halfword, Word, and Write hold state until next cycle. DS506PP1 t MOEd EXs EXh C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) High-Performance, Low-Power System on Chip t CSh t MOEh t Dh EP7311 19 ...
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... EP7311 High-Performance, Low-Power System on Chip Static Memory Single Write Cycle EXPCLK nCS A nMWE nMOE t HWd HALF- WORD t WDd WORD D EXPRDY WRITE Note: 1. The cycle time can be extended by integer multiples of the clock period ( MHz MHz 18.432 MHz, and MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK before the data transfer ...
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... Address, Halfword, Word, and Write hold state until next cycle. DS506PP1 EXs EXh Figure 9. Static Memory Burst Read Cycle Timing Measurement C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) High-Performance, Low-Power System on Chip t CSh MOEh EP7311 21 ...
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... EP7311 High-Performance, Low-Power System on Chip Static Memory Burst Write Cycle EXPCLK t CSd nCS MWd nMWE nMOE t HWd HALF WORD t WORD WDd EXs EXPRDY WRITE Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-1-1-1). This is the maximum number of consecutive cycles that can be driven ...
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... INh Figure 11. SSI1 Interface Timing Measurement C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) High-Performance, Low-Power System on Chip Symbol Min Max INs INh − Ovd − Ovd EP7311 Unit ...
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... EP7311 High-Performance, Low-Power System on Chip SSI2 Interface Parameter SSICLK period (slave mode) SSICLK high time SSICLK low time SSICLK rise/fall time SSICLK rising edge to RX and/or TX frame sync high time SSICLK rising edge to RX and/or TX frame sync low time SSIRXFR and/or SSITXFR period ...
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... High-Performance, Low-Power System on Chip Symbol t CL2d t FRMd t Md Figure 13. LCD Controller Timing Measurement C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) Min Max − CL1d t 80 3,475 CL2d t 300 10,425 FRMd − − DDd EP7311 Unit ...
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... EP7311 High-Performance, Low-Power System on Chip JTAG Interface Parameter TCK clock period TCK clock high time TCK clock low time JTAG port setup time JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance ...
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... LQFP Pin 1 Indicator 1.35 (0.053) 0.45 (0.018) 1.45 (0.057) 0.75 (0.030) Figure 15. 208-Pin LQFP Package Outline Drawing Figure 16. For pin descriptions see the EP7311 User’s Manual. C opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) High-Performance, Low-Power System on Chip 27.80 (1.094) 28.20 (1.110) 1.00 (0.039) BSC 0° ...
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... Figure 16. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram Note: 1. N/C should not be grounded but left as no connects. 2. Pin differences between the EP7211 and the EP7311 are bolded. 28 EP7311 208-Pin LQFP (Top View) C opyright Cirrus Logic, Inc. 2003 © ...
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... PD[3] I/O 1 PD[2] I/O 1 PD[1] I/O 1 I/O 1 SSICLK I/O 1 VSSIO Pad Gnd SSITXFR I/O 1 SSITXDA O 1 SSIRXDA I SSIRXFR I/O ADCIN I nADCCS O 1 Core Gnd Core Pwr VSSIO Pad Gnd EP7311 Reset State Input Input Input Low Low Low Low Low Low Low Low Input Low Low Input High 29 ...
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... EP7311 High-Performance, Low-Power System on Chip Table T. 208-Pin LQFP Numeric Pin Listing (Continued) Pin Signal Type No. 74 VDDIO Pad Pwr 75 DRIVE[1] I/O 76 DRIVE[0] I/O 77 ADCCLK O 78 ADCOUT O 79 SMPCLK O 80 FB[ VSSIO Pad Gnd 82 FB[ COL[ COL[ COL[ COL[ COL[3] ...
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... VSSIO Pad Gnd SDCKE I/O 2 SDCLK I VSSIO Pad Gnd nCS[ nCS[ nCS[ nCS[ nCS[ EP7311 Reset State Low Low Low Low Low High High Low Low Low Low High High High High High High High 31 ...
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... EP7311 High-Performance, Low-Power System on Chip 204-Ball TFBGA Package Characteristics 204-Ball TFBGA Package Specifications TOP VIEW A1 CORNER SEATING PLANE Figure 17. 204-Ball TFBGA Package C opyright Cirrus Logic, Inc. 2003 © ...
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... D17 D18 A19/ DRA8 D21 HALF WORD A26/ BUZ D29 VDDIO DRA1 A27/ COL5 COL2 COL0 D30 D26 DRA0 COL6 COL3 COL1 D31 D28 D27 EP7311 19 20 GNDIO GNDIO A GNDIO nURESET B BATOK nPOR D10 F A9 D11 G D12 A12 ...
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... EP7311 High-Performance, Low-Power System on Chip 204-Ball TFBGA Ball Listing The list is ordered by ball location. Table 21. 204-Ball TFBGA Ball Listing Ball Location Name Strength A1 VDDIO A2 EXPCLK A3 nCS[3] A4 nCS[1] A5 nMWE/nSDWE A6 SDQM[2] A7 nSDCS[1] A8 DD[2] A9 FRM A10 CL[1] A11 VSSCORE A12 D[1] A13 A[2] A14 D[4] A15 A[5] A16 nPWRFL ...
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... Chip select 4 Chip select 0 SDRAM clock out SDRAM byte lane mask LCD serial display data LCD serial display data Digital core power, 2.5 V System byte address Data I/O System byte address Data I/O System byte address PLL ground Oscillator power in, 2.5V I/O ground Battery ok input EP7311 35 ...
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... EP7311 High-Performance, Low-Power System on Chip Table 21. 204-Ball TFBGA Ball Listing (Continued) Ball Location Name Strength C20 nPOR D1 PB[7] D2 RXD[2] D3 VDDIO D18 VSSIO D19 nBATCHG D20 A[7] E1 PB[4] E2 TXD[2] E3 WRITE/nSDRAS E18 nMEDCHG/nBROM E19 nEXTPWR E20 D[9] F1 PB[3] F2 PB[6] F3 TDI F18 D[7] F19 A[8] F20 D[10] G1 PB[1] G2 PB[2] G3 PB[5] G18 D[8] G19 ...
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... System byte address / SDRAM address UART 1 receive data input UART 1 clear to send input GPIO port A System byte address / SDRAM address System byte address / SDRAM address JTAG async reset input UART 1 data set ready input Test mode select input Photodiode input EP7311 37 ...
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... EP7311 High-Performance, Low-Power System on Chip Table 21. 204-Ball TFBGA Ball Listing (Continued) Ball Location Name Strength N18 D[17] N19 D[19] N20 A[18]/DRA[9] P1 EINT[3] P2 nEINT[2] P3 DCD P18 D[18] P19 A[20]/DRA[7] P20 D[20] R1 nEXTFIQ R2 PE[2]/CLKSEL R3 nTEST[0] R18 A[19]/DRA[8] R19 D[22] R20 A[21]/DRA[6] T1 PE[1]/BOOTSEL[1] T2 PE[0]/BOOTSEL[0] T3 nEINT[1] T18 D[21] T19 D[23] T20 A[22]/DRA[5] ...
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... Data I/O System byte address / SDRAM address Digital I/O power, 3.3 V Digital I/O power, 3.3 V System byte address / SDRAM address I/O ground I/O ground I/O ground GPIO port D / SDRAM byte lane mask JTAG mode select GPIO port D DAI/CODEC/SSI2 frame sync DAI/CODEC/SSI2 frame sync Core Ground PWM drive output EP7311 39 ...
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... EP7311 High-Performance, Low-Power System on Chip Table 21. 204-Ball TFBGA Ball Listing (Continued) Ball Location Name Strength W11 ADCOUT W12 FB[0] W13 COL[5] W14 COL[2] W15 COL[0] W16 D[30] W17 A[27]/DRA[0] W18 D[26] W19 VDDIO W20 D[25] Y1 VSSIO Y2 VSSIO Y3 VSSIO Y4 PD[5] Y5 PD[3] Y6 PD[0]/LEDFLSH Y7 SSITXDA Y8 ADCIN Y9 VDDCORE Y10 DRIVE[0] ...
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... PBGA Package Characteristics 256-Ball PBGA Package Specifications Note: 1) For pin locations see Table 2) Dimensions are in millimeters (inches), and controlling dimension is millimeter 3) Before beginning any new EP7311 design, contact Cirrus Logic for the latest package information. 256-Ball PBGA Pinout (Top View ...
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... EP7311 High-Performance, Low-Power System on Chip Pin 1 Corner 17.00 (0.669) E1 ±0.20 (.008) 15.00 (0.590) ±0.20 (.008) 1.00 (0.040) REF 1.00 (0.040) REF 1.00 (0.040) 0. Places 42 17.00 (0.669) ±0.20 (.008) 15.00 (0.590) ±0.20 (.008) D1 Pin 1 Indicator TOP VIEW D 17.00 (0.669) 1.00 (0.040 ...
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... Pad ground I/O ground Media change interrupt input / internal I ROM boot enable VDDIO Pad power Digital I/O power, 3.3V D[9] I/O Data I/O D[10] I/O Data I/O PB[5] I GPIO port B PB[3] I GPIO port B VSSIO Pad ground I/O ground TXD[2] O UART 2 transmit data output O Run output / clock enable output VSSIO Pad ground I/O ground EP7311 43 ...
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... EP7311 High-Performance, Low-Power System on Chip Table V. 256-Ball PBGA Ball Listing (Continued) Ball Location Name Type F7 SDCKE O SDRAM clock enable output F8 DD[3] O LCD serial display data F9 A[1] O System byte address F10 D[6] I/O Data I/O F11 VSSRTC RTC ground Real time clock ground F12 BATOK ...
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... MCP/CODEC/SSI2 serial clock – MCP/CODEC/SSI2 frame sync Core power Core power, 2.5V I/O PWM drive output FB[1] I PWM feedback input COL[5] O Keyboard scanner column drive VDDIO Pad power Digital I/O power, 3.3V BUZ O Buzzer drive output D[28] I/O Data I/O O System byte address / SDRAM address D[25] I/O Data I/O VSSIO Pad ground I/O ground EP7311 45 ...
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... EP7311 High-Performance, Low-Power System on Chip JTAG Boundary Scan Signal Ordering LQFP TFBGA Pin No Table W. JTAG Boundary Scan Signal Ordering PBGA Signal Ball ...
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... High-Performance, Low-Power System on Chip Type Position I 79 I/O 80 I/O 83 I/O 86 I/O 89 I/O 92 I/O 95 I/O 98 I/O 101 I/O 104 I/O 107 O 110 I/O 122 I 125 O 126 I/O 128 I/O 131 O 134 O 136 O 138 I 140 I 141 O 142 O 144 O 146 O 148 O 150 O 152 O 154 O 156 O 158 I/O 160 I/O 163 I/O 166 I/O 169 Out 172 I/O 174 O 177 EP7311 47 ...
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... EP7311 High-Performance, Low-Power System on Chip LQFP TFBGA Pin No. 102 103 104 105 106 109 110 111 112 113 114 115 117 118 119 120 121 122 126 127 128 129 130 131 132 133 134 135 136 137 138 141 142 ...
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... Type Position O 274 I/O 276 I 279 I 280 I 281 I 282 I 283 I 284 I 285 I 286 O 287 I/O 289 O 292 I/O 294 O 297 I/O 299 O 302 I/O 304 O 307 I/O 309 O 312 I/O 314 O 317 I/O 319 O 322 O 324 O 326 O 328 I/O 330 I/O 333 I/O 336 I/O 339 O 342 O 344 I/O 346 I/O 349 I/O 352 I/O 355 EP7311 49 ...
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... TFBGA Pin No. 201 202 204 205 206 207 208 1) See EP7311 Users’ Manual for pin naming / functionality. 2) For each pad, the JTAG connection ordering is input, output, then enable as applicable. 50 Table W. JTAG Boundary Scan Signal Ordering (Continued) PBGA Signal Ball Ball ...
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... opyright Cirrus Logic, Inc. 2003 © (All Rights Reserved) EP7311 Definition test access port translation lookaside buffer universal asynchronous receiver Table Y. Unit of Measurement Unit of Measure degree Celsius sample frequency hertz (cycle per second) kilobits per second ...
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... Registers are referred to by acronym, with bits listed in brackets separated by a colon (:) (for example, CODR[7:0]), and are described in the EP7311 User’s Manual. The use of “TBD” indicates values that are “to be determined,” “n/a” designates “not available,” and “ ...
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... ORDERING INFORMATION The order number for the device is: EP7311 — CV — C Note: Contact Cirrus Logic for up-to-date information on revisions the Cirrus Logic Internet site at http://cirrus.com/corporate/contacts to find contact information for your local sales representative. DS506PP1 High-Performance, Low-Power System on Chip Package Type: ...
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... EP7311 High-Performance, Low-Power System on Chip Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided " ...