AT80F51-12AI ATMEL [ATMEL Corporation], AT80F51-12AI Datasheet - Page 4

• Manufacturer Part Number: AT80F51-12AI
• Description: 8-Bit Microcontroller with 4K Bytes QuickFlash Memory
• Manufacturer: ATMEL [ATMEL Corporation]

cycle, except that two PSEN activations are skipped during
each access to external data memory.
EA
External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external pro-
gram memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA will be
internally latched on reset.
EA should be strapped to V
tions.
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively,
of an inverting amplifier which can be configured for use as
an on-chip oscillator, as shown in Figure 1. Either a quartz
crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven as shown in Figure 2.
There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuitry
is through a divide-by-two flip-flop, but minimum and maxi-
mum voltage high and low time specifications must be
observed.
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-
chip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and all the spe-
cial functions registers remain unchanged during this
mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
It should be noted that when idle is terminated by a hard
ware reset, the device normally resumes program execu-
tion, from where it left off, up to two machine cycles before
the internal reset algorithm takes control. On-chip hardware
inhibits access to internal RAM in this event, but access to
the port pins is not inhibited. To eliminate the possibility of
Status of External Pins During Idle and Power Down Modes
3-6
Mode
Idle
Idle
Power Down
Power Down
Program Memory
Internal
External
Internal
External
CC
AT80F51
for internal program execu-
ALE
1
1
0
0
PSEN
an unexpected write to a port pin when Idle is terminated by
reset, the instruction following the one that invokes Idle
should not be one that writes to a port pin or to external
memory.
Figure 1. Oscillator Connections
Note:
Figure 2. External Clock Drive Configuration
Power Down Mode
In the power down mode the oscillator is stopped, and the
instruction that invokes power down is the last instruction
executed. The on-chip RAM and Special Function Regis-
ters retain their values until the power down mode is termi-
1
1
0
0
C1, C2 = 30 pF
PORT0
Float
Float
Data
Data
= 40 pF
C2
C1
PORT1
Data
Data
Data
Data
10 pF for Crystals
10 pF for Ceramic Resonators
Address
PORT2
Data
Data
Data
XTAL2
XTAL1
GND
PORT3
Data
Data
Data
Data