TSC80251-SK TEMIC [TEMIC Semiconductors], TSC80251-SK Datasheet - Page 31

• Manufacturer Part Number: TSC80251-SK
• Description: 8/16-bit Microcontroller with Serial Communication Interfaces
• Manufacturer: TEMIC [TEMIC Semiconductors]

TSC80251G2D
Notes:
1. Signature Bytes are not user-programmable.
2. The ALE/PROG# pulse waveform is shown in Figure 31 page 54.
8.5 Verify Algorithm
Figure 10 shows the hardware setup needed to verify the TSC87251G2D EPROM/OTPROM or TSC83251G2D
ROM areas:
31
On-chip Code Memory
Configuration Bytes
Lock Bits
Encryption Array
The chip has to be put under reset and maintained in this state until the completion of the verifying sequence.
PSEN# and the other control signals (ALE and Port 0) have to be set to a high level.
Then PSEN# has to be to forced to a low level after two clock cycles or more and it has to be maintained in
this state until the completion of the verifying sequence (see below).
The voltage on the EA# pin must be set to V
The Verifying Mode is selected according to the code applied on Port 0. It has to be applied until the completion
of this verifying operation.
The verifying address is applied on Ports 1 and 3 which are respectively the MSB and the LSB of the address.
Then device is driving the data on Port 2.
It is possible to alternate programming and verification operation (see Paragraph 8.4). Please make sure the
voltage on the EA# pin has actually been lowered to V
PSEN# and the other control signals have to be released to complete a sequence of verifying operations or a
sequence of programming and verifying operations.
ROM Area
(1)
RST
100 s pulses
1
1
1
1
A[14:8]
A[7:0]
Mode
Data
EA#/VPP
V
PP
VDD
V
V
V
V
PP
PP
PP
PP
Figure 9. Setup for Programming
Table 38. Programming Modes
P3[7:0]
P1[7:0]
RST
EA#/VPP
ALE/PROG#
PSEN#
P0[7:0]
P2[7:0]
PSEN# ALE/PROG#
0
0
0
0
DD
TSC87251G2D
and ALE must be set to a high level.
VSS/VSS1/VSS2
1 Pulse
1 Pulse
1 Pulse
1 Pulse
DD
before performing the verifying operation.
XTAL1
VDD
(2)
VDD
6Bh
6Ch
68h
69h
P0
4 to 12 MHz
Data
Data
Data
P2
X
0000h-7FFFh (32 Kbytes)
P1(MSB) P3(LSB)
Rev. A - May 7, 1999
CONFIG0: FFF8h
CONFIG1: FFF9h
16-bit Address
0000h-007Fh
LB0: 0001h
LB1: 0002h
LB2: 0003h