TSC80251-SK TEMIC [TEMIC Semiconductors], TSC80251-SK Datasheet - Page 7

• Manufacturer Part Number: TSC80251-SK
• Description: 8/16-bit Microcontroller with Serial Communication Interfaces
• Manufacturer: TEMIC [TEMIC Semiconductors]

Rev. A - May 7, 1999
PROG#
Signal
PSEN#
Name
P1.0:7
P2.0:7
P3.0:7
T2EX
VDD
RXD
SDA
TXD
RD#
SCK
T1:0
RST
SCL
VPP
SS#
T2
Type
PWR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
I
I
I
Port 1
Port 2
Port 3
Programming Pulse input
Program Store Enable/Read signal output
Read or 17
Reset input to the chip
Receive Serial Data
I
SPI Serial Clock
I
SPI Slave Select Input
Timer 1:0 External Clock Inputs
Timer 2 Clock Input/Output
Timer 2 External Input
Transmit Serial Data
Digital Supply Voltage
Programming Supply Voltage
2
2
C Serial Clock
C Serial Data
P1 is an 8-bit bidirectional I/O port with internal pull-ups. P1 provides interrupt capability
for a keyboard interface.
P2 is an 8-bit bidirectional I/O port with internal pull-ups.
P3 is an 8-bit bidirectional I/O port with internal pull-ups.
The programming pulse is applied to this input for programming the on-chip EPROM/
OTPROM.
PSEN# is asserted for a memory address range that depends on bits RD0 and RD1 in
UCONFIG0 byte (see Table 13, Page 15).
Read signal output to external data memory depending on the values of bits RD0 and RD1
in UCONFIG0 byte (see Table 13, Page 15).
Holding this pin high for 64 oscillator periods while the oscillator is running resets the device.
The Port pins are driven to their reset conditions when a voltage greater than V
whether or not the oscillator is running.
This pin has an internal pull-down resistor which allows the device to be reset by connecting
a capacitor between this pin and VDD.
Asserting RST when the chip is in Idle mode or Power-Down mode returns the chip to normal
operation.
RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1,
2 and 3.
When I
When I
When SPI is in master mode, SCK outputs clock to the slave peripheral. When SPI is in
slave mode, SCK receives clock from the master controller.
SDA is the bidirectional I
When in Slave mode, SS# enables the slave mode.
When timer 1:0 operates as a counter, a falling edge on the T1:0 pin increments the count.
For the timer 2 capture mode, T2 is the external clock input. For the Timer 2 clock-out mode,
T2 is the clock output.
In timer 2 capture mode, a falling edge initiates a capture of the timer 2 registers. In auto-
reload mode, a falling edge causes the timer 2 register to be reloaded. In the up-down counter
mode, this signal determines the count direction: 1= up, 0= down.
TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O modes 1,
2 and 3.
Connect this pin to +5V or +3V supply voltage.
The programming supply voltage is applied to this input for programming the on-chip EPROM/
OTPROM.
th
2
2
C controller is in slave mode, SCL receives clock from the master controller.
C controller is in master mode, SCL outputs the serial clock to slave peripherals.
Address Bit (A16)
2
C data line.
Description
TSC80251G2D
IH1
is applied,
A15:8
P3.7
P3.0
P1.6
P1.6
P1.7
P1.4
P1.0
P1.1
P3.1
Alternate
Function
7