AT87F55WD ATMEL [ATMEL Corporation], AT87F55WD Datasheet - Page 23

• Manufacturer Part Number: AT87F55WD
• Manufacturer: ATMEL [ATMEL Corporation]

Serial Port Timing: Shift Register Mode Test Conditions
The values in this table are valid for V
Shift Register Mode Timing Waveforms
AC Testing Input/Output Waveforms
Note:
Symbol
t
t
t
t
t
XLXL
QVXH
XHQX
XHDX
XHDV
V
CC
INSTRUCTION
WRITE TO SBUF
- 0.5V
0.45V
OUTPUT DATA
INPUT DATA
1.
CLEAR RI
AC Inputs during testing are driven at V
for a logic 1 and 0.45V for a logic 0. Timing mea-
surements are made at V
max. for a logic 0.
CLOCK
Parameter
Serial Port Clock Cycle Time
Output Data Setup to Clock Rising Edge
Output Data Hold After Clock Rising Edge
Input Data Hold After Clock Rising Edge
Clock Rising Edge to Input Data Valid
ALE
0.2 V
0.2 V
TEST POINTS
0
CC
CC
t
QVXH
+ 0.9V
- 0.1V
IH
min. for a logic 1 and V
CC
t
= 4.0V to 5.5V and Load Capacitance = 80 pF.
1
XHDV
0
VALID
CC
- 0.5V
2
t
XLXL
t
1
XHQX
VALID
(1)
IL
3
t
Min
700
1.0
XHDX
2
50
Float Waveforms
Note:
12 MHz Osc
0
VALID
V
LOAD
4
1.
3
Max
700
VALID
V
V
LOAD
LOAD
For timing purposes, a port pin is no longer floating
when a 100 mV change from load voltage occurs. A
port pin begins to float when a 100 mV change from
the loaded V
5
+ 0.1V
- 0.1V
4
VALID
10t
2t
12t
CLCL
CLCL
Min
Variable Oscillator
OH
0
CLCL
Timing Reference
6
(1)
-133
-80
/V
5
OL
VALID
Points
level occurs.
7
10t
6
VALID
CLCL
Max
-133
SET TI
SET RI
8
V
V
OL
OL
7
VALID
- 0.1V
+ 0.1V
Units
µs
ns
ns
ns
ns
23