M37733 MITSUBISHI [Mitsubishi Electric Semiconductor], M37733 Datasheet - Page 13

• Manufacturer Part Number: M37733
• Description: 16-BIT CMOS MICROCOMPUTER
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

____
HLDA
when the microcomputer receives
____
HOLD
microcomputer in hold state.
clock
P0
P2
microcomputer stays in hold state. These pins are floating after one
cycle of the internal clock
level. At the removing of hold state, these ports are removed from
floating state after one cycle of internal clock
changes to “H” level.
___
RDY
stops at “L”.
P4
independent of
stops because of “L” input to the
output can also be stopped with the signal output disable selection
bit “1”. In this case, write “1” to the port P4
(2) Evaluation chip mode [11]
Evaluation chip mode is entered by applying voltage twice the V
voltage to the CNV
tools.
The functions of
are the same as those in microprocessor mode.
P1
_
E
of the BYTE pin level. However, if an internal memory is read, external
data is ignored while
as address output pins while
addresses while
an internal memory is read, external data is ignored while
When the BYTE pin level is “H” or 2•V
address output pin while
addresses while
external data is ignored while
Port P4 and its data direction which are located at address 0A
0C
Table 2. Function of signal output disable selection bit CM
Note. Functions shown in Table 2 cannot be emulated in a debugger.
Microprocessor mode
is “H” and as data I/O pin of odd addresses while
7
0
0
2
16
/A
/A
/A
/
is a ready signal. If this signal goes “L”, the internal clock
are treated differently in evaluation chip mode. When these
0
23
8
Processor mode
is a hold acknowledge signal and is used to notify externally
is a hold request signal. It is an input signal used to put the
/D
to P0
/D
1
falls from “H” level to “L” level while the bus is not used.
8
7
pin is an output pin for clock
to P1
pins, P3
7
___
RDY
/A
___
RDY
7
7
_
E
/A
_
E
pins, P1
_
E
, P0
is used when slow external memory is attached.
SS
15
is “L” when the BYTE pin level is “L”. However, if
0
is “L”. However, if an internal memory is read,
/R/
and does not stop even when internal clock
/D
_
E
pin. This mode is normally used for evaluation
0
/A
15
is “L”. P2
_
W
_
E
0
0
pins function as address output pins while
pin, and P3
is “H” and as data I/O pin of even and odd
/A
to P0
_
____
HOLD
_
E
8
/D
later than
_
E
_
E
1
7
8
is “L”.
0
is “H” and as data I/O pin of even
/A
___
RDY
/A
to P1
input is accepted when the internal
____
HOLD
7
16
Pin
pins, R/
/D
1
pin. As shown in Table 2,
/
___
BHE
7
0
CC
/A
____
HLDA
input and enters hold state.
to P2
15
2
, port P2 functions as an
pin are floating while the
/D
direction register.
W
_ ___
1
,
signal changes to “L”
15
7
later than
. The
BHE
/A
pins, P2
23
E
_
E
area is accessed.
After WIT/STP instruction is executed,
“H” is output.
Clock
/D
, ALE, and
is “L” regardless
is output when the internal/external memory
7
pins function
____
HLDA
1
0
/A
output is
_
E
6
1
16
is “L”.
(bit 6 of oscillation circuit control register 0)
is output.
16
/D
signal
____
HLDA
and
0
CC
to
1
CM
6
= “0”
addresses are accessed, the data bus width is treated as 16 bits
regardless of the BYTE pin level, and the access cycle is treated as
internal memory regardless of the wait bit.
The functions of
microprocessor mode. Clock
regardless of signal output disable selection bit.
Ports P4
respectively. Port P4
The MX signal normally contents of flag m, but the contents of flag x
is output if the CPU is using flag x.
QCL is the queue buffer clear signal. It becomes “H” when the
instruction queue buffer is cleared, for example, when a jump
instruction is executed.
VDA is the valid data address signal. It becomes “H” while the CPU
is reading data from data buffer or writing data to data buffer. It also
becomes “H” when the first byte of the instruction (operation code) is
read from the instruction queue buffer.
VPA is the valid program address signal. It becomes “H” while the
CPU is reading an instruction code from the instruction queue buffer.
___
DBC
shows the relationship between the CNV
processor modes.
Table 1. Relationship between CNVss pin input levels and processor
CNVss
2 • Vcc
is the debug control signal and is used for debugging. Table 1
Vss
3
modes
to P4
6
• Evaluation chip
• Microprocessor
(• Evaluation chip)
Function
become MX, QCL, VDA, and VPA output pins
HOLD
____
7
becomes the
MITSUBISHI MICROCOMPUTERS
_
E
area is accessed.
“L” is output after WIT/STP instruction is
executed.
“H”or “L” is output. (Output the content of
P4
Mode
“1”.
function control register) must be set to “1”.
Port P4
is output only when the external memory
Standby state selection bit (bit 0 of port
2
and
16-BIT CMOS MICROCOMPUTER
latch.)
1
RDY
___
2
from P4
direction register must be set to
___
DBC
M37733S4BFP
are the same as those in
Microprocessor mode upon
starting after reset.
Evaluation chip mode only.
CM
input pin.
2
/
SS
6
= “1”
1
pin input levels and
Description
pin is always output
13