X40410 INTERSIL [Intersil Corporation], X40410 Datasheet
X40410
Related parts for X40410
X40410 Summary of contents
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... Instrumentation • Computer Systems —Computers —Network Servers DESCRIPTION The X40410/11/14/15 combines power-on reset con- trol, watchdog timer, supply voltage supervision, and secondary voltage supervision, and Block Lock tect serial EEPROM in one package. This combination lowers system cost, reduces board space require- ments, and increases reliability ...
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... V2MON comparator is supplied by V2MON (X40410/11 RESET/ RESET Output. (X40411/15) This is an active LOW, open drain output which goes active whenever V falls below V RESET CC RESET Output. (X40410/14) This is an active HIGH CMOS output which goes active whenever V falls below Ground SDA Serial Data ...
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... V CC PRINCIPLES OF OPERATION Power-On Reset Application of power to the X40410/11/14/15 activates a Power-on Reset Circuit that pulls the RESET/RESET pins active. This signal provides several benefits. – It prevents the system microprocessor from starting to operate with insufficient voltage. – It prevents the processor from operating prior to stabili- zation of the oscillator. – ...
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... WDO signal going active. The state of two nonvolatile control bits in the Status Register determines the watchdog timer period. The microprocessor can change these watchdog bits by writing to the X40410/11/14/15 control register (also refer to page 19). Figure 3. Watchdog Restart .6µs 1.3µ ...
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... The user must issue a stop, after sending this byte to the register, to initiate the nonvolatile cycle that stores WD1, WD0, PUP1, PUP0, BP1, and BP0. The X40410/11/14/15 will not acknowledge any data bytes written after the first byte is entered. becomes a nomi- The state of the Control Register can be read at any time by performing a random read at address 01Fh, using the special preamble ...
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... While the WEL bit is LOW, writes to any address, including any control registers will be ignored (no acknowledge will be issued after the Data Byte). The WEL bit is set by writing a “1” to the WEL bit and zeros to the other bits of the control register. 6 X40410, X40411, X40414, X40415 V Programming TRIPX Desired No ...
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... This is also a volatile cycle. The zeros in the data byte are required. (Operation proceeded by a start and ended with a stop). 7 X40410, X40411, X40414, X40415 – Write a one byte value to the Control Register that has all the control bits set to the desired state. The Control register can be represented as qxys 001r in binary, where xy are the WD bits, s isthe BP bit and qr are the power-up bits ...
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... LV2F, Low V2MON Reset Fail Bit (Volatile) The LV2F bit will be set to “0” when V2MON falls below V . TRIP2 8 X40410, X40411, X40414, X40415 Data Stable Data Change SERIAL INTERFACE Interface Conventions The device supports a bidirectional bus oriented proto- col. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver ...
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... Master Data Output from Data Output from Receiver Start 9 X40410, X40411, X40414, X40415 Start detected. The master must then issue a stop condition to return the device to Standby mode and place the device into a known state. Serial Write Operations Byte Write For a write operation, the device requires the Slave Address Byte and a Word Address Byte ...
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... Figure 11. Writing 12 bytes to a 16-byte page starting at location 10. 7 Bytes address = 6 The master terminates the Data Byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. As with the byte write operation, 10 X40410, X40411, X40414, X40415 S t Slave Byte a Address Address ...
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... See Figure 13 for the address, acknowledge, and data transfer sequence. 11 X40410, X40411, X40414, X40415 Figure 12. Acknowledge Polling Sequence It should be noted that the ninth clock cycle of the read operation is not a “don’t care.” To terminate a read ...
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... Where x=0 is for Array, x=1 is for Control Register or Fault Detection Register. – next two bits are ‘0’. – next bit that becomes the MSB of the address. Figure 13. X40410/11 Addressing General Purpose Memory Control Register Fault Detection Register General Purpose Memory ...
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... SDA pin is the input mode. – RESET/RESET Signal is active for Figure 16. Sequential Read Sequence Slave Signals from Address the Master SDA Bus Signals from K the Slave 13 X40410, X40411, X40414, X40415 S Slave Byte t a Address Address ...
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... SET/RESET, V2FAIL, WDO) V Output (RESET) HIGH Voltage OH 14 X40410, X40411, X40414, X40415 COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied ...
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... See Ordering Information for standard programming levels. For custom programmed levels, contact factory. (6) Based on characterization data. EQUIVALENT INPUT CIRCUIT FOR VxMON ( ∆V V VxMON ref CAPACITANCE Symbol (1) C Output Capacitance (SDA, RESET, RESET, V2FAIL, OUT WDO) (1) C Input Capacitance (SCL) IN Note: (1) This parameter is not 100% tested. 15 X40410, X40411, X40414, X40415 (Continued) (4) Min. Typ. 2.0 4.55 4.6 4.35 4.4 2.85 2.9 2.55 2.6 1.7 0.9 2.85 2.9 2.55 2.6 1.65 1 ...
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... SDA WDO 30pF 30pF A.C. TEST CONDITIONS Input pulse levels V Input rise and fall times 10ns Input and output timing levels V Output load Standard output load 16 X40410, X40411, X40414, X40415 SYMBOL TABLE WAVEFORM V2MON 4.6kΩ V2FAIL 30pF 0.5 CC INPUTS ...
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... SDA and SCL Fall Time F Cb Capacitive load for each bus line Note: ( total capacitance of one bus line in pF. TIMING DIAGRAMS Bus Timing t F SCL t SU:STA t HD:STA SDA IN SDA OUT 17 X40410, X40411, X40414, X40415 Parameter t t HIGH LOW t SU:DAT t HD:DAT 400kHz Min. Max. 0 400 50 0.1 0.9 1 ...
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... Acknowledge Polling is used. Power Fail Timings TRIPX [ ] V2MON [ ] LOWLINE or V2FAIL or V3FAIL X40410, X40411, X40414, X40415 ACK Stop Condition Parameter Min. t RPDL t RPDX t RPDL t RPDX V RVALID t WC Start ...
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... RST1 WD1=0, WD0=0 WD1=0, WD0=1 t Watchdog Reset Time Out Delay WD1=1, WD0=0 RST2 t Watchdog timer restart pulse width RSP Notes: ( 25°C. CC (2) Values based on characterization data only. 19 X40410, X40411, X40414, X40415 t RPD1 Parameters t PURST t F (1) Min. Typ. Max ...
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... SCL SDA WDO Minimum Sequence to Reset WDT SCL SDA V Set/Reset Conditions TRIPX (V TRIPX t TSU WDO t VPS SCL 0 SDA A0h Start 20 X40410, X40411, X40414, X40415 Start Clockin ( RSP < t WDO Start ) V /V2MON resets V 01h* 03h* sets V TRIP1 ...
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... Program Voltage Off time before next cycle VPO V Programming Voltage Set Voltage Range TRAN1 TRIP1 V V Set Voltage Range – X40410/11 TRAN2 TRIP2 V V Set to Voltage Range – X40414/15 TRAN2A TRIP2 V V Set Voltage variation after programming (-40 to +85°C). tv TRIPX ...
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... PACKAGING INFORMATION Pin 1 Index 0.050 (1.27) 0.010 (0.25) 0.020 (0.50) 0° - 8° 0.016 (0.410) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 22 X40410, X40411, X40414, X40415 8-Lead Plastic, SOIC, Package Code S8 Pin 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7° 0.004 (0.19) 0.010 (0.25) X 45° 0.0075 (0.19) 0.250" ...
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... PACKAGING INFORMATION 0° – 8° .019 (.50) .029 (.75) Detail A (20X) See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 23 X40410, X40411, X40414, X40415 8-Lead Plastic, TSSOP, Package Code V8 .025 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .114 (2.9) .122 (3.1) .047 (1.20) .0075 (.19) .002 (.05) .006 (.15) ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 24 X40410, X40411, X40414, X40415 Operating Temperature Range ...