X40430 INTERSIL [Intersil Corporation], X40430 Datasheet
X40430
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X40430 Summary of contents
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... Servers 1 X40430, X40431, X40434, X40435 July 29, 2005 DESCRIPTION The X40430, X40431, X40434, X40435 combines power-on reset control, watchdog timer, supply voltage supervision, second and third voltage supervision, manual reset, and Block Lock in one package. This combination lowers system cost, reduces board space requirements, and increases reliability ...
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... V2 Voltage Monitor Input. When the V2MON input is less than the V This input can monitor an unregulated power supply with an external resistor divider or can monitor a second power supply with no external components. Connect V2MON to V V2MON comparator is supplied by V2MON (X40430, X40431 the V 3 LOWLINE Early Low V Detect ...
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... RESET Output. (X40431, X40435) This open drain pin is an active LOW output which goes LOW when- ever V falls below V RESET CC grammed time period (t t thereafter. PURST RESET Output. (X40430, X40434) This pin is an active HIGH CMOS output which goes HIGH when- ever V falls below V CC grammed time period (t t thereafter. PURST 7 ...
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... CC for . t PURST Low Voltage V2 Monitoring The X40430 also monitors a second voltage level and asserts V2FAIL if the voltage falls below a preset mini- mum V . The V2FAIL signal is either ORed with TRIP2 RESET to prevent the microprocessor from operating in a power fail or brownout condition or used to inter- rupt the microprocessor with notification of an impend- ing power failure ...
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... Figure 4. Watchdog Restart .6µs 1.3µs SCL SDA Start WDT Reset V1, V2 AND V3 THRESHOLD PROGRAM PROCEDURE (OPTIONAL) The X40430 is shipped with standard V1, V2 and V3 threshold ( TRIP1, TRIP2, TRIP3 values will not change over normal operating and stor- age conditions. However, in applications where the ...
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... Control Registers" on page 7. The user must issue a stop, after sending this byte to the register, to initiate the nonvolatile cycle that stores WD1, WD0, PUP1, PUP0, and BP. The X40430, X40431, X40434, X40435 will not acknowledge any data bytes written after the first byte is entered. ...
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... WEL bit and zeroes to the other bits of the control register) or until the part powers up again. Writes to the WEL bit do not cause a high volt- age write cycle, so the device is ready for the next operation immediately after the stop condition. 7 X40430, X40431, X40434, X40435 V Programming TRIPX Desired No V < ...
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... Figure 7. Valid Data Changes on the SDA Bus SCL SDA 8 X40430, X40431, X40434, X40435 nonvolatile write cycle it will take up to 10ms (max.) to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the non- volatile bits again. If bit 2 is set to ‘1’ in this third step ...
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... TRIP3 Figure 8. Valid Start and Stop Conditions SCL SDA 9 X40430, X40431, X40434, X40435 SERIAL INTERFACE Interface Conventions The device supports a bidirectional bus oriented proto- col. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver ...
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... Signals from the Master SDA Bus Signals from the Slave 10 X40430, X40431, X40434, X40435 detected. The master must then issue a stop condition to return the device to Standby mode and place the device into a known state. Serial Write Operations Byte Write For a write operation, the device requires the Slave Address Byte and a Word Address Byte ...
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... Figure 12. Writing 12 bytes to a 16-byte page starting at location 10. 7 Bytes address = 6 11 X40430, X40431, X40434, X40435 Stops and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ACK signal stop is ...
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... SDA HIGH during the ninth clock cycle and then issue a stop condition. 12 X40430, X40431, X40434, X40435 Random Read Random read operation allows the master to access any memory location in the array. Prior to issuing the Slave Address Byte with the R/W bit set to one, the master must first perform a “ ...
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... Where for Array for Control Register or Fault Detection Register. – next two bits are ‘0’. – next bit that becomes the MSB of the address. Figure 14. X40430, X40431, X40434, X40435 Addressing Slave Byte General Purpose Memory 1 ...
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... Master r t SDA Bus Signals from the Slave Figure 17. Sequential Read Sequence Slave Signals from Address the Master SDA Bus Signals from K the Slave 14 X40430, X40431, X40434, X40435 S Slave Byte t a Address Address ...
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... V3FAIL, WDO) V Output (RESET, LOWLINE) HIGH OH Voltage 15 X40430, X40431, X40434, X40435 COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied ...
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... Based on characterization data. EQUIVALENT INPUT CIRCUIT FOR VxMON ( ∆V V VxMON ref CAPACITANCE Symbol (1) C Output Capacitance (SDA, RESET/RESET, LOWLINE, OUT V2FAIL,V3FAIL, WDO) (1) C Input Capacitance (SCL, WP, MR) IN Note: (1) This parameter is not 100% tested. 16 X40430, X40431, X40434, X40435 (Continued) (4) Min Typ 2.0 4.55 4.6 4.35 4.4 2.85 2.9 1.7 0.9 2.85 2.9 2.55 2.6 2.15 2.2 1 ...
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... SDA and SCL Fall Time Setup Time SU: Hold Time HD:WP Cb Capacitive load for each bus line Note: ( total capacitance of one bus line in pF. 17 X40430, X40431, X40434, X40435 SYMBOL TABLE WAVEFORM V2MON, V3MON 4.6kΩ V2FAIL, V3FAIL 30pF ...
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... the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. 18 X40430, X40431, X40434, X40435 t t HIGH ...
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... V V2MON V3MON F CC V2MON V3MON R CC Reset Valid V RVALID CC ( RESET/ RESET delay (activation only X40430, X40431, X40434, X40435 t RPDL t RPDX t RPDL t RPDX V RVALID t RPD1 IN1 Parameters to V3FAIL ( TRIP3 Fall Time Rise Time t RPDL t RPDX ...
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... Notes: ( 25°C. CC (2) Values based on characterization data only. Watchdog Time Out For 2-Wire Interface Start SCL SDA WDO Minimum Sequence to Reset WDT SCL SDA 20 X40430, X40431, X40434, X40435 Parameters Start Clockin ( RSP < t WDO Start = 5V) (CONTINUED) CC (1) ...
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... TRIPX t Program Voltage Off time before next cycle VPO V Programming Voltage Set Voltage Range TRAN1 TRIP1 V V Set Voltage Range – X40430, X40431 TRAN2 TRIP2 V V Set to Voltage Range – X40434, X40435 TRAN2A TRIP2 V V Set Voltage Range TRAN3 TRIP3 V V Set Voltage variation after programming (-40 to +85° ...
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... Pin 1 0.014 (0.35) 0.020 (0.51) 0.336 (8.55) 0.345 (8.75) (4X) 7° 0.050 (1.27) 0.010 (0.25) 0.020 (0.50) 0° – 8° 0.016 (0.410) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 22 X40430, X40431, X40434, X40435 0.150 (3.80) 0.158 (4.00) 0.004 (0.10) 0.010 (0.25) X 45° 0.250" 0.0075 (0.19) 0.010 (0.25) FOOTPRINT 0.228 (5.80) 0.244 (6.20) 0.053 (1.35) 0.069 (1.75) 0.050" ...
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... PACKAGING INFORMATION 0° - 8° See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 23 X40430, X40431, X40434, X40435 14-Lead Plastic, TSSOP, Package Type V .025 (.65) BSC .169 (4.3) .177 (4.5) .193 (4.9) .200 (5.1) .0075 (.19) .002 (.05) .0118 (.30) .006 (.15) .010 (.25) .019 (.50) .029 (.75) Detail A (20X) .252 (6.4) BSC .047 (1.20) ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 24 X40430, X40431, X40434, X40435 Operating V Temperature ...