X51638S8 INTERSIL [Intersil Corporation], X51638S8 Datasheet - Page 2

• Manufacturer Part Number: X51638S8
• Description: CPU Supervisor with 16Kbit SPI EEPROM Description
• Manufacturer: INTERSIL [Intersil Corporation]

Block Diagram
Pin Description
(SOIC/PDIP)
CS/WDI
V
SCK
PIN
CC
SO
1
2
3
4
5
6
7
8
WP
SI
PIN TSSOP
3-5,10-12
13
14
1
2
6
7
8
9
V
CC
Reset Logic
Command
Decode &
2
Register
Control
Threshold
Logic
Data
CS/WDI
RESET/
RESET
NAME
SCK
V
V
WP
SO
NC
SI
SS
CC
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance
state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode.
CS LOW enables the device, placing it in the active power mode. Prior to the start of any
operation after power-up, a HIGH to LOW transition on CS is required
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The
absence of a HIGH to LOW transition within the watchdog time out period results in
RESET/RESET going active.
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The
falling edge of the serial clock (SCK) clocks the data out.
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the Watchdog Timer control and the memory write protect bits.
Ground
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this
pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.
Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge
of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK
changes the data output on the SO pin.
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active
whenever V
the minimum V
RESET goes active if the Watchdog Timer is enabled and CS remains either HIGH or LOW longer
than the selectable Watchdog time out period. A falling edge of CS will reset the Watchdog Timer.
RESET/RESET goes active on power-up at 1V and remains active for 200ms after the power
supply stabilizes.
Supply Voltage
No internal connections
Watchdog Transition
V
Detector
TRIP
CC
X5163, X5165
CC
Protect Logic
falls below the minimum V
Register
4K Bits
4K Bits
8K Bits
sense level for 200ms. RESET/
Status
+
-
Timer Reset
Power-on and
Low Voltage
Watchdog
CC
Generation
Watchdog
Timebase
FUNCTION
Reset &
Reset
sense level. It will remain active until V
RESET/RESET
X5163 = RESET
X5165 = RESET
CC
rises above
May 16, 2005
FN8128.1