ATA5724 ATMEL [ATMEL Corporation], ATA5724 Datasheet - Page 21

• Manufacturer Part Number: ATA5724
• Description: UHF ASK/FSK Receiver
• Manufacturer: ATMEL [ATMEL Corporation]

9106E–RKE–07/08
Figure 9-3.
Figure 9-4.
The delay of the data clock is calculated as follows: t
t
depends on the capacitive load C
falling edge, t
on page 22
Data_Out, the data clock is issued after an additional delay t
Note that the capacitive load at pin DATA is limited. If the maximum tolerated capacitive load at
pin DATA is exceeded, the data clock disappears (see
Delay1
Data_out (DATA)
Data_out (DATA)
DATA_CLK
DATA_CLK
is the delay between the internal signals Data_Out and Data_In. For the rising edge, t
Dem_out
Dem_out
and
Delay1
Data Clock Disappears Because of a Logical Error
Output of the Data Clock After a Successful Bit Check
Figure 13-2 on page
depends additionally on the external voltage V
'1'
'1'
Receiving mode,
Bit check ok
data clock control
bit check active
Receiving mode,
logic active
'1'
'1'
'1'
'1'
L
at pin DATA and the external pull-up resistor R
30). When the level of Data_In is equal to the level of
'0'
'1'
ATA5723/ATA5724/ATA5728
'1'
'1'
Start bit
Delay
Logical error (Manchester code violation)
'1'
'0'
Data
Data
Section 14. “Data Interface” on page
= t
Delay1
'?'
'1'
Delay2
data clock control
Receiving mode,
.
+ t
logic active
'0'
'1'
X
Delay2
(see
'0'
'0'
Figure
Receiving mode,
bit check active
'1'
'1'
9-5,
pup
Figure 9-6
'0'
'0'
. For the
Delay1
32).
21