ATA5756-6DPY ATMEL [ATMEL Corporation], ATA5756-6DPY Datasheet
ATA5756-6DPY
Related parts for ATA5756-6DPY
ATA5756-6DPY Summary of contents
Page 1
... PLL Transmitter IC with Single-ended Output • High Output Power (6 dBm) at 8.1 mA (315 MHz) and 8.5 mA (433 MHz) Typical Values • Divide by 24 (ATA5756) and 32 (ATA5757) Blocks for 13 MHz Crystal Frequencies and for Low XTO Start-up Times • Modulation Scheme ASK/FSK with Internal FSK Switch • ...
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... Switches off the FSK switch (switch has high Z if signal at pin FSK is High) and 3 FSK enables the PLL and the XTO if the ENABLE pin is open ATA5756/ATA5757 CLK ASK 2 9 ATA5756 FSK 3 8 ATA5757 ANT2 4 7 ANT1 5 6 /8. XTAL ENABLE GND ...
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... ENABLE input If ENABLE is connected to GND and the ASK or FSK pin is High, the device 10 ENABLE stays in idle mode. In normal operation ENABLE is left open and ASK or FSK is used to enable the device. 4702J–RKE–09/08 ATA5756/ATA5757 Configuration (FSK < 0.25V) AND (ENABLE > 1.7V) XTO2 VS 1.5k XTO1 182 µA ...
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... CLK output activation. This means an additional wait time of ≥250 µs is necessary before the PA can be switched on and the data transmission can start. This results in a signifi- cantly lower time of about 0.85 ms between enabling the ATA5756/ATA5757 and the beginning of the data transmission which saves battery power especially in tire pressure monitoring systems ...
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... Table 4-1. ASK Pin Low Low Low High High Low/High High 4702J–RKE–09/08 = 380 Ω + j340 Ω (ATA5756) at 315 MHz and Z ATA5756/ATA5757 Modes FSK Pin ENABLE Pin Low Low/open Low High High High/open Low High/open ...
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... Transmission with ENABLE = open 4.1.1 ASK Mode The ATA5756/ATA5757 is activated by ENABLE = open, FSK = High, ASK = Low. The microcon- troller is then switched to external clocking. After typically 0.6 ms, the CLK driver is activated automatically (i.e., the microcontroller waits until the XTO and CLK are ready). After another time period of modulated by means of pin ASK ...
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... Figure 4-3. 4.2.2 ASK Mode The ATA5756/ATA5757 is activated by ENABLE = High, FSK = High and ASK = Low. After acti- vation the microcontroller is switched to external clocking. After typically 0.6 ms, the CLK driver is activated automatically (the microcontroller waits until the XTO and CLK are ready). After another time period of then be modulated by means of pin ASK ...
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... Using a crystal with a motional capacitance LNOM = 297 × internal FSK switch with C the resulting C deviation of ±19.3 kHz with worst case tolerances of ±15.8 kHz to ±23.2 kHz. ATA5756/ATA5757 8 Timing ASK Mode with ENABLE Connected to the Microcontroller ΔT XTO ENABLE FSK ASK CLK ...
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... The clock of the crystal oscillator can be used for clocking the microcontroller. Atmel’s ATARx9x microcontroller family provides the special feature of starting with an integrated RC oscillator to switch on the ATA5756/ATA5757’s external clocking and to wait automatically until the CLK out- put of the ATA5756/ATA5757 is activated. After a time period of 250 µs the message can be sent with crystal accuracy. 4.5.2 Output Matching and Power Setting The output power is set by the load impedance of the antenna ...
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... The 0.66 pF output capacitance absorbed into the load impedance a real impedance of 684 Ω (ATA5756) at 315 MHz and 623 Ω (ATA5757) at 433.92 MHz should be measured with a net- work analyses at pin 5 (ANT1) with the ATA5756/ATA5757 soldered, an optimized antenna connected and the power amplifier switched off. ...
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... For the supply voltage blocking capacitor C 4-7 on page 12 the power amplifier. For C ance value and to enable it to realize Z Together with the pins of ATA5756 and the PCB board wires, C that suppresses the 1 the best suppression is achieved when C ANT2. The loop antenna should not exceed a width of 1.5 mm, otherwise the Q-factor of the loop antenna is too high ...
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... Figure 4-7. ASK Application Circuit Loop C1 Antenna L1 VS ATA5756/ATA5757 12 BPXY ATARx9x BPXY BPXY OSC1 7 ATA5756/ATA5757 Power up/down EN CLK 24/ ASK PFD FSK 3 CP ANT2 ANT1 5 VCO PA PLL VDD 1 VS VSS 20 BPXY ENABLE 10 GND Ampl. OK XTO1 XTAL ...
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... L1 VS 4702J–RKE–09/08 BPXY ATARx9x BPXY BPXY OSC1 7 ATA5756/ATA5757 Power up/down EN CLK 24/ ASK PFD FSK 3 CP ANT2 ANT1 5 VCO PA PLL ATA5756/ATA5757 VDD 1 VS VSS 20 BPXY ENABLE 10 GND Ampl. OK XTO1 XTAL XTO 7 XTO2 ...
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... S V < 0. ENABLE is open, ENABLE V < 0. < 0.25 V ASK FSK Input voltage Note 0.3 is higher than 3.7 V, the maximum voltage will be reduced to 3 Thermal Resistance Parameters Junction ambient ATA5756/ATA5757 14 ASK FSK Symbol tot stg T amb1 ≤ 3 amb2 ...
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... ATA5756 /24 XTO 0 ATA5757 /32 XTO resonant frequency of the XTAL = 4.37 fF, load capacitance XTAL selected accordingly T = -40°C to +85°C amb T = -40°C to +125°C amb ATA5756/ATA5757 ≤ Ω Symbol Min. Typ S_Off I S_IDLE I 3 S_Transmit1 8.1 8.5 I S_Transmit2 8.4 8 ...
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... Time between the activation of CLK and when the PLL is locked (transmitter ready for data transmission) 25 kHz distance to carrier at 1 MHz at 36 MHz ATA5756 ATA5757 ATA5756 ATA5757 ≤ 20 pF, High = 0.8 × Vs, C Load Low = 0.2 × < 1.7 MHz S CLK For proper detection of the XTO ...
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... Low level input voltage High level input voltage Input current high Low level input voltage High level input voltage Input current high Low level input voltage High level input voltage Input current high Input current Low ATA5756/ATA5757 ≤ Ω Symbol Min. Typ ...
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... Ordering Information Extended Type Number ATA5756-6DQY ATA5756-6DPY ATA5757-6DQY ATA5757-6DPY 9. Package Information TSSOP10 Package: TSSOP 10 (acc. to JEDEC Standard MO-187) Dimensions in mm Not indicated tolerances ± 0.05 0.5 nom 0 nom. ATA5756/ATA5757 18 Package Remarks TSSOP10 Pb-free TSSOP10 Pb-free 3 ±0.1 0. ±0.1 3.8 ± ...
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... ATA5756/ATA5757 History • Put datasheet in a new template • Page1: PB-free logo deleted • Page 18: Ordering Information changed • Put datasheet in a new template • First page: Pb-free logo added • Page 18: Ordering Information and package drawing changed • ...
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