X5043 XICOR [Xicor Inc.], X5043 Datasheet - Page 5

• Manufacturer Part Number: X5043
• Description: CPU Supervisor with 4K SPI EEPROM
• Manufacturer: XICOR [Xicor Inc.]

X5043/X5045
Figure 4. V
Table 1. Instruction Set
Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
REV 1.1.2 5/29/01
Instruction Name
New V
Old V
Error
WRITE
WREN
WRSR
- Error
RSDR
READ
CC
WRDI
CC
=
Applied
Applied
TRIP
-Emax
NO
Emax = Maximum Desired Error
Programming Sequence
Set V
V
(V
TRIP
Apply 5V to V
Decrement V
CC
Measured V
CC
Desired V
-Desired V
Instruction Format*
goes active?
Reset V
RESET pin
Sequence
Sequence
Set V
= V
Execute
Execute
= V
Programming
DONE
0000 A
0000 A
CC
CC
0000 0110
0000 0100
0000 0101
0000 0001
TRIP
YES
-Emax < Error < Emax
TRIP
–10mV)
TRIP
Applied =
TRIP
TRIP
CC
CC
8
8
011
010
New V
Old V
Error
Reset V
Sequence
Execute
- Error
CC
CC
=
Set the Write Enable Latch (Enable Write Operations)
Reset the Write Enable Latch (Disable Write Operations)
Read Status Register
Write Status Register (Watchdog and Block Lock)
Read Data from Memory Array Beginning at Selected Address
Write Data to Memory Array Beginning at Selected Address (1 to 16 bytes)
Emax
Applied
Applied
TRIP
www.xicor.com
SPI Serial Memory
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s block lock protection. The
array is internally organized as x8 bits. The device fea-
tures a Serial Peripheral Interface (SPI) and software
protocol allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families.
The device contains an 8-bit instruction register that
controls the operation of the device. The instruction
code is written to the device via the SI input. There are
two write operations that requires only the instruction
byte. There are two read operations that use the
instruction byte to initiate the output of data. The
remainder of the operations require an instruction byte,
an 8-bit address, then data bytes. All instruction,
address and data bits are clocked by the SCK input. All
instructions (Table 1), addresses and data are trans-
ferred MSB first.
Clock and Data Timing
Data input on the SI line is latched on the first rising
edge of SCK after CS goes LOW. Data is output on the
SO line by the falling edge of SCK. SCK is static,
allowing the user to stop the clock and then start it
again to resume operations where left off. CS must be
LOW during the entire operation.
Operation
Characteristics subject to change without notice.
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