X5001P INTERSIL [Intersil Corporation], X5001P Datasheet - Page 5

• Manufacturer Part Number: X5001P
• Description: CPU Supervisor
• Manufacturer: INTERSIL [Intersil Corporation]

Figure 4. V
SPI INTERFACE
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families.
The device monitors the CS/WDI line and asserts
RESET output if there is no activity within user select-
able time out period. The device also monitors the V
supply and asserts the RESET if V
preset minimum (V
TRIP
Programming Sequence
Old V
New V
TRIP
CC
). The device contains an 8-bit
CC
Applied + Error
Applied =
5
Error < 0
CC
falls below a
NO
Set V
(V
V
Apply 5V to V
CC
Decrement V
CC
TRIP
Measured V
Desired V
CC
Reset V
goes active?
Desired V
RESET pin
Sequence
Sequence
Set V
X5001
= V
Execute
Execute
= V
Programming
DONE
CC
CC
TRIP
TRIP
YES
Error = 0
- 50mV)
Applied =
TRIP
TRIP
TRIP
CC
watchdog timer register to control the watchdog time
out period. The current settings are accessed via the
SI and SO pins.
All instructions (Table 1) and data are transferred MSB
first. Data input on the SI line is latched on the first ris-
ing edge of SCK after CS goes LOW. Data is output
on the SO line by the falling edge of SCK. SCK is
static, allowing the user to stop the clock and then start
it again to resume operations where left off.
CC
-
Error > 0
Old V
New V
CC
Reset V
Sequence
CC
Execute
Applied - Error
Applied =
TRIP
April 6, 2005
FN8125.0