U5021M_05 ATMEL [ATMEL Corporation], U5021M_05 Datasheet - Page 7
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U5021M_05
Manufacturer Part Number
U5021M_05
Description
Digital Window Watchdog Timer
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.U5021M_05.pdf
(11 pages)
Figure 5-1.
4756D–AUTO–11/05
State Diagram
Notes:
"mode" and "trg" are the debounced input signals from the pins MODE and TRG
trg_ok = 1 after the rising edge of the trg signal
trg_err = 1 when the trg signal low period is too long
wedge = 1 after detecting the debounced changing of a signal level from the WUP pin
Every state change restarts the internal timer
If a state change is generated from an external debounced pin signal exactly one clock cycle before the internal
timer initiates a state change itself, the state machine changes its state twice. The first state change is created
by the signal change, and the second by the timeout of the internal timer. This occurs due to the timer getting
its reset one clock cycle after a state change.
time out t
Mode switch
Reset state
Reset out
time out t
state
state
time out t
6
0
1
trg = 0
mode = 0
trg_err = 1
time out t
trg_ok = 1
3
time out t
wedge = 1
Short window
Short window
disable state
enable state
time out t
or
5
2
mode = 1
trg_err = 1
mode = 1
mode = 0
mode = 0
or wedge = 1
Long window
Long window
trg = 0
disable state
enable state
time out t
4
trg_ok = 1
U5021M
7