X4163 INTERSIL [Intersil Corporation], X4163 Datasheet

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X4163

Manufacturer Part Number
X4163
Description
CPU Supervisor with 16K EEPROM
Manufacturer
INTERSIL [Intersil Corporation]
Datasheets

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CPU Supervisor with 16K EEPROM
FEATURES
• Selectable watchdog timer
• Low V
• Low power CMOS
• 16Kbits of EEPROM
• Built-in inadvertent write protection
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available Packages
BLOCK DIAGRAM
—Four standard reset threshold voltages
—Adjust low V
—Reset signal valid to V
—<20µA max standby current, watchdog on
—<1µA standby current, watchdog OFF
—3mA active current
—64-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
—Power-up/power-down protection circuitry
—Block Lock (1, 2, 4, 8 pages, all, none)
—8-lead SOIC
—8-lead TSSOP
V
SDA
SCL
special programming sequence
CC
WP
S0
S1
CC
detection and reset assertion
CC
reset threshold voltage using
V
Reset logic
CC
®
Command
Decode &
Register
Control
Threshold
Data
Logic
1
CC
Watchdog Transition
= 1V
Data Sheet
Detector
V
TRIP
EEPROM Array
1-888-INTERSIL or 1-888-352-6832
Protect Logic
Register
+
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Status
-
DESCRIPTION
The X4163/5 combines four popular functions, Power-
on Reset Control, Watchdog Timer, Supply Voltage
Supervision, and Serial EEPROM Memory in one pack-
age. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
The device’s low V
user’s system from low voltage conditions, resetting the
system when V
point. RESET/RESET is asserted until V
proper operating level and stabilizes. Four industry
standard V
sil’s unique circuits allow the threshold to be repro-
grammed to meet custom requirements or to fine-tune
the threshold for applications requiring higher precision.
Power on and
Timer Reset
Low Voltage
out
Generation
Watchdog
Watchdog
All other trademarks mentioned are the property of their respective owners.
Timebase
April 13, 2005
Reset &
Reset
|
TRIP
Intersil (and design) is a registered trademark of Intersil Americas Inc.
interval,
CC
thresholds are available, however, Inter-
Copyright Intersil Americas Inc. 2005. All Rights Reserved
falls below the set minimum V
CC
detection circuitry protects the
the
X4163, X4165
device
16K, 2K x 8 Bit
RESET (X4163)
RESET (X4165)
activates
CC
FN8120.0
returns to
CC
the
trip

Related parts for X4163

X4163 Summary of contents

Page 1

... Reset logic DESCRIPTION The X4163/5 combines four popular functions, Power- on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Serial EEPROM Memory in one pack- age. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power on reset circuit which holds RESET/RESET active for a period of time ...

Page 2

... SDA 6 8 SCL X4163, X4165 SCL SDA SCL SDA V SS RESET/RESET Device Select Input Device Select Input Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever V falls below the minimum V ...

Page 3

... PRINCIPLES OF OPERATION Power On Reset Application of power to the X4163/5 activates a Power On Reset Circuit that pulls the RESET/RESET pin active. This signal provides several benefits. – It prevents the system microprocessor from starting to operate with insufficient voltage. – It prevents the processor from operating prior to sta- bilization of the oscillator. – ...

Page 4

... A0h Figure 3. Sample V Reset Circuit TRIP 4.7K RESET V TRIP Adj. 4 X4163, X4165 Resetting the higher or This procedure is used to set the V TRIP voltage level. For example, if the current V and the new V be reset. When V thing less than 1.7V. This procedure must be used to TRIP set the voltage to a lower value ...

Page 5

... The state of the Control Register can be read at any time by performing a random read at address FFFFh. Only one byte is read by each register read operation. The X4163/5 resets itself after the first byte is read. The master should supply a stop condition to be con- sistent with the bus protocol, but a stop is not required to end this operation ...

Page 6

... HIGH 0 HIGH 1 6 X4163, X4165 again. Writes to the WEL bit do not cause a nonvolatile write cycle, so the device is ready for the next opera- tion immediately after the stop condition. WD1, WD0: Watchdog Timer Bits The bits WD1 and WD0 control the period of the Watchdog Timer ...

Page 7

... Figure 5. Valid Data Changes on the SDA Bus SCL SDA 7 X4163, X4165 – The RWEL bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block. To illustrate, a sequence of writes to the device con- sisting of [02H, 06H, 02H] will reset all of the nonvola- tile bits in the Control Register to 0 ...

Page 8

... Transmitter Data Output from Receiver Start 8 X4163, X4165 Start mitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 7. The device will respond with an acknowledge after ...

Page 9

... Figure 9. Page Write Operation S t Signals from a the Master Slave r Address t SDA Bus Signals from the Slave 9 X4163, X4165 Slave Word Address Address Byte Page Write The device is capable of a page write operation initiated in the same manner as the byte write opera- tion ...

Page 10

... ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation. Refer to the flow chart in Figure 11. 10 X4163, X4165 Address Pointer Address Ends Here 60 Addr = 8 Figure 11 ...

Page 11

... Figure 13. Random Address Read Sequence S Signals from t a Slave the Master r Address t SDA Bus Signals from the Slave 11 X4163, X4165 Slave r Address Random Read Random read operation allows the master to access any memory location in the array. Prior to issuing the Slave Address Byte with the R/W bit set to one, the master must first perform a “ ...

Page 12

... Data Data K (1) (2) X4163/5 Addressing S LAVE Following a start condition, the master must output a Slave Address Byte. This byte consists of several parts: – a device type identifier that is ‘1010’ to access the array. – one bits of ‘0’. – next two bits are the device address. ...

Page 13

... Figure 15. X4163/5 Addressing Device Identifier (X1) (X0 Operational Notes The device powers-up in the following state: – The device is in the low power standby state. – The WEL bit is set to ‘0’. In this state it is not possi- ble to write to the device. ...

Page 14

... Min. and V Max. are for reference only and are not tested X4163, X4165 COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied ...

Page 15

... Cb Capacitive load for each bus line Notes: (1) Typical values are for T = 25°C and total capacitance of one bus line in pF. 15 X4163, X4165 = 5V) CC Parameter A.C. TEST CONDITIONS Input pulse levels Input rise and fall times Input and output timing levels For ...

Page 16

... the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. 16 X4163, X4165 t t HIGH LOW ...

Page 17

... R RESET (X4165) RESET (X4163) RESET Output Timing Symbol V Reset Trip Point Voltage, X4163/5-4.5A TRIP Reset Trip Point Voltage, X4163/5 Reset Trip Point Voltage, X4163/5-2.7A Reset Trip Point Voltage, X4163/5-2.7 t Power-up Reset Time Out PURST ( Detect to Reset/Output RPD CC ( Fall Time ...

Page 18

... Program Voltage repeatability (Successive program operations. Programmed tr TRIP at 25°C Program variation after programming (0-75°C). (Programmed at 25°C.) tv TRIP V programming parameters are periodically sampled and are not 100% tested. TRIP 18 X4163, X4165 Min. 100 450 1 100 V TRIP t TSU 01h or 03h 00h 00h ...

Page 19

... PACKAGING INFORMATION 8-Lead Plastic Small Outline Gull Wing Package Type S Pin 1 Index 0.050 (1.27) 0.010 (0.25) 0.020 (0.50) 0° - 8° 0.016 (0.410) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 19 X4163, X4165 Pin 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7° 0.004 (0.19) 0.010 (0.25) X 45° 0.0075 (0.19) 0.250" ...

Page 20

... PACKAGING INFORMATION 0° - 8° .019 (.50) .029 (.75) Detail A (20X) See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 20 X4163, X4165 8-Lead Plastic, TSSOP, Package Type V .025 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .114 (2.9) .122 (3.1) .047 (1.20) .0075 (.19) .002 (.05) .006 (.15) .0118 (.30) .010 (.25) Gage Plane Seating Plane ...

Page 21

... X4163S8–2.7 -40°C - 85°C X4163S8I–2.7 0°C - 70°C X4163V8–2.7 -40°C - 85°C X4163V8I–2.7 8-Lead SOIC X4163 -4. +70° -4.5A (-40 to +85°C) Blank = No Suffix (0 to +70° Suffix (-40 to +85° -2. +70° -2.7A (-40 to +85° -2 +70° -2.7 (-40 to +85°C) ...

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