XC6118 TOREX [Torex Semiconductor], XC6118 Datasheet - Page 12

• Manufacturer Part Number: XC6118
• Description: Voltage Detector with Separated Sense Pin & Delay Capacitor Pin
• Manufacturer: TOREX [Torex Semiconductor]

④ When the sense pin voltage continues to increase up to the release voltage level (V
⑤ While the delay capacitance pin voltage (V
⑥ When the delay capacitance pin voltage reaches to the delay capacitance pin threshold voltage (V
⑦ While the sense voltage is higher than the detect voltage (V
●Function Chart
●Release Delay Time Chart
12/20
*1: V
* The release delay time values above are calculated by using the formula (2).
*2: The release delay time (t
●Example
ex. 1) V
ex. 2) V
■OPERATIONAL EXPLANATION (Continued)
* Note that the release delay time may remarkably be short when the delay capacitance (Cd) is not discharged to the ground
CAPACITANCE [Cd]
The release delay time can also be briefly calculated with the formula (2) because the delay resistance is 2.0MΩ(TYP.) and
the delay capacitance pin voltage is V
As an example, presuming that the delay capacitance is 0.68μF, t
the delay capacitance (Cd) discharge will be turned OFF, and the delay capacitance (Cd) will start discharging via a delay
resistor (Rdelay).
Threshold: V
sense pin voltage equal to the release voltage or higher, the sense pin will be charged by the time constant of the RC series
circuit. Assuming the time to the release delay time (t
capacitance pin voltage becomes the input voltage level. Therefore, the output voltage maintains the “High”(=V
XC6118
(=V
(Inv.1) will be inverted. As a result, the output voltage changes into the “High” (=V
ranges from V
OUT
V
H
SEN
L
SS
OUT
OUT
DELAY
transits from condition ① to ② because of the combination of V
0.010
0.022
0.047
0.100
0.220
0.470
1.000
(μF)
) level because time described in ③ is short.
maintains ‘H’ when Cd ranges from ‘H’ to ‘L’, V
ranges from ‘L’ to ‘H’ in case of V
THL
SEN
=V
=V
SS
Cd
Series
The inverter (Inv
H
H
H
H
L
L
L
L
DF
) while the sense pin voltage keeps higher than the detect voltage (V
DR
+V
) is influenced by the delay capacitance Cd.
HYS
RELEASE DELAY TIME [t
to the V
TRANSITION OF V
①
SEN
H
H
L
L
IN /2
.
t
OUT
1) will operate as a comparator (Rise Logic Threshold: V
DR
2.0
1380
(TYP.)
13.8
30.4
64.9
138
304
649
= ‘H’ (V
(ms)
=-R
(TYP.)
×
of “High” level without connecting to the Cd.
t
CD
*
DR
：
10
delay
) rises to reach the delay capacitance pin threshold voltage (V
=R
R
DR
6
delay
SEN
×
×
delay
≧V
0.68
Cd
=’H’ and Cd=’L’ when V
×
is 2.0M
SEN
⇒
⇒
⇒
⇒
DR
DR
OUT
×
Cd
×
), it can be given by the formula (1).
]
), Cd=’H’ (V
ln(1-V
CONDITION *1
10
×
SEN
Ω（
0.69
-6
×
SEN
> V
TCD
0.69=938(ms)
DR
TYP.
DF
and Cd.
TCD
/V
is :
…
), the delay capacitance pin is charged until the delay
IN
②
H
L
L
≧Cd) while V
(2)
)
）
OUT
…
RELEASE DELAY TIME [t
becomes ‘H’ in ex.1.
(1)
1100 ~ 1660
(MIN. ~ MAX.)
24.3 ~ 36.4
51.9 ~ 77.8
11.0 ~ 16.6
OUT
IN
243 ~ 364
519 ~ 778
110 ~ 166
DF
) level. t
+V
(ms)
is ‘L’.
HYS
SEN
), the N-ch transistor (M1) for
> V
DR0
DF
is defined as time which
DR
CD
).
TLH
] *2
=V
=V
TCD
TCD
), the inverter
TCD
, Fall Logic
IN
) with the
) level.