S-1170 SII [Seiko Instruments Inc], S-1170 Datasheet - Page 10

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S-1170

Manufacturer Part Number
S-1170
Description
HIGH RIPPLE-REJECTION AND LOW DROPOUT HIGH OUTPUT CURRENT CMOS VOLTAGE REGULATOR
Manufacturer
SII [Seiko Instruments Inc]
Datasheet

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10
HIGH RIPPLE-REJECTION LOW DROPOUT HIGH OUTPUT CURRENT CMOS VOLTAGE REGULATOR
S-1170 Series
Standard Circuit
Application Conditions
Selection of Input and Output Capacitors (C
Caution The above connection diagram and constant will not guarantee successful operation.
Input capacitor (C
Output capacitor (C
ESR of output capacitor:
Caution A general series regulator may oscillate, depending on the external components selected.
The S-1170 Series requires an output capacitor between the VOUT and VSS pins for phase compensation.
A ceramic capacitor with a capacitance of 4.7 µF or more provides a stable operation in all temperature
ranges. When using an OS capacitor, tantalum capacitor, or aluminum electrolytic capacitor, a ceramic
capacitor with a capacitance of 4.7 µF or more and an ESR of 0.5 Ω or less is required.
The output overshoot and undershoot values, which are transient response characteristics, vary depending
on the output capacitor value. The required capacitance value for the input capacitor differs depending on
the application.
The recommended application values are, C
a thorough evaluation using the actual device, including evaluation of temperature characteristics.
Perform thorough evaluation using the actual application to set the constant.
Check that no oscillation occurs with the application using the above capacitor.
IN
):
L
):
Input
4.7 µF or more
4.7 µF or more
0.5 Ω or less
*1. C
*2. A ceramic capacitor of 4.7 µF or more can be used for C
C
IN
IN
*1
is a capacitor for stabilizing the input.
Single GND
Seiko Instruments Inc.
IN
ON/OFF
VIN
= 4.7 µF or more and C
Figure 10
VSS
VOUT
IN
, C
L
)
GND
C
L
*2
Output
L
= 4.7 µF or more, however, perform
L
.
Rev.3.0
_02

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