XR16C2850CM48 EXAR [Exar Corporation], XR16C2850CM48 Datasheet - Page 7

• Manufacturer Part Number: XR16C2850CM48
• Description: 3.3V AND 5V DUART WITH 128-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

XR16C2850
REV. 2.0.0
The CPU interface is 8 data bits wide with 3 address
lines and control signals to execute data bus read and
write transactions. The 2850 data interface supports
the Intel compatible types of CPUs and it is compati-
ble to the industry standard 16C550 UART. No clock
The RESET input resets the internal registers and the
serial interface outputs in both channels to their de-
fault state (see Table 16 on page 30). An active high
pulse of longer than 40 ns duration will be required to
activate the reset function in the device.
The XR16C2850 provides a Device Identification
code and a Device Revision code to distinguish the
part from other devices and revisions. To read the
identification code from the part, it is required to set
the baud rate generator registers DLL and DLM both
to 0x00. Now reading the content of the DLM will pro-
vide 0x12 for the XR16C2850 and reading the con-
tent of DLL will provide the revision of the part; for ex-
ample, a reading of 0x01 means revision A.
The UART provides the user with the capability to bi-
directionally transfer information between an external
2.0 FUNCTIONAL DESCRIPTIONS
2.1 CPU I
2.2 D
2.3 D
2.4 C
EVICE
EVICE
HANNEL
F
IGURE
NTERFACE
U AR T_R ESET
R
I
U AR T_C SA#
U AR T_C SB#
DENTIFICATION AND
U AR T_IN TA
U AR T_IN TB
ESET
A
R XR D YA#
R XR D YB#
TXR D YA#
TXR D YB#
3.
AND
IOW#
IOR #
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
A0
A1
A2
XR16C2850 D
B S
ELECTION
3.3V AND 5V DUART WITH 128-BYTE FIFO
R
EVISION
ATA
B
US
I
NTERCONNECTIONS
7
(oscillator nor external clock) is required to operate a
data bus transaction. Each bus cycle is asynchronous
using CS#, IOR# and IOW# signals. Both UART
channels share the same data bus for host opera-
tions. The data bus interconnections are shown in
Figure 3.
CPU and an external serial communication device. A
logic 0 on chip select pins, CSA# or CSB#, allows the
user to select UART channel A or B to configure,
send transmit data and/or unload receive data to/from
the UART. Selecting both UARTs can be useful dur-
ing power up initialization to write to the same internal
registers, but do not attempt to read from both uarts
simultaneously. Individual channel select functions
are shown in Table 1.
IOR #
IOW#
C SA#
C SB#
R ESET
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
IN TA
IN TB
TXR D YA#
R XR D YA#
TXR D YB#
R XR D YB#
A0
A1
A2
CSA#
1
0
1
0
C hannel A
C hannel B
U AR T
U AR T
T
ABLE
D TR A#
D SR A#
D TR B#
D SR B#
R TSA#
C TSA#
R TSB#
C TSB#
OP2A#
1: C
C D A#
OP2B#
C D B#
CSB#
GN D
VC C
R IA#
R IB#
TXA
R XA
TXB
R XB
1
1
0
0
HANNEL
VC C
Serial Interface of R S-
Serial Interface of
R S-232, R S-485
Channel A and B selected
232, R S-485
A
AND
Channel A selected
Channel B selected
UART de-selected
B S
F
2750int
UNCTION
ELECT